{"id":2197347,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2197347/?format=json","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/1.0/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260217173457.18628-2-akhilrajeev@nvidia.com>","date":"2026-02-17T17:34:50","name":"[1/8] dt-bindings: dma: nvidia,tegra186-gpc-dma: Add iommu-map property","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"cbc7615e4b32cac9508a62c7e90b4896805d46e1","submitter":{"id":81965,"url":"http://patchwork.ozlabs.org/api/1.0/people/81965/?format=json","name":"Akhil R","email":"akhilrajeev@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260217173457.18628-2-akhilrajeev@nvidia.com/mbox/","series":[{"id":492464,"url":"http://patchwork.ozlabs.org/api/1.0/series/492464/?format=json","date":"2026-02-17T17:34:49","name":"Add GPCDMA support in Tegra264","version":1,"mbox":"http://patchwork.ozlabs.org/series/492464/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2197347/checks/","tags":{},"headers":{"Return-Path":"\n <linux-tegra+bounces-12012-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=fZ/YzftF;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF 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<linux-tegra@vger.kernel.org>","CC":"<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<vkoul@kernel.org>, <Frank.Li@kernel.org>, <robh@kernel.org>,\n\t<krzk+dt@kernel.org>, <conor+dt@kernel.org>, <thierry.reding@gmail.com>,\n\t<jonathanh@nvidia.com>, <p.zabel@pengutronix.de>, Akhil R\n\t<akhilrajeev@nvidia.com>","Subject":"[PATCH 1/8] dt-bindings: dma: nvidia,tegra186-gpc-dma: Add iommu-map\n property","Date":"Tue, 17 Feb 2026 23:04:50 +0530","Message-ID":"<20260217173457.18628-2-akhilrajeev@nvidia.com>","X-Mailer":"git-send-email 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Feb 2026 17:35:53.4493\n (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 439babef-e381-4df8-7c2b-08de6e4afffe","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n\tSJ1PEPF00002313.namprd03.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DS4PR12MB9562"},"content":"Add iommu-map property which helps when each channel requires its own\nstream ID for the transfer. Use iommu-map to specify separate stream\nID for each channel. This enables each channel to be in its own iommu\ndomain and keeps the memory isolated from other devices sharing the\nsame DMA controller.\n\nSigned-off-by: Akhil R <akhilrajeev@nvidia.com>\n---\n .../devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml  | 8 ++++++++\n 1 file changed, 8 insertions(+)","diff":"diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml\nindex 0dabe9bbb219..542e9cb9f641 100644\n--- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml\n+++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml\n@@ -14,6 +14,7 @@ description: |\n maintainers:\n   - Jon Hunter <jonathanh@nvidia.com>\n   - Rajesh Gumasta <rgumasta@nvidia.com>\n+  - Akhil R <akhilrajeev@nvidia.com>\n \n allOf:\n   - $ref: dma-controller.yaml#\n@@ -51,6 +52,13 @@ properties:\n   iommus:\n     maxItems: 1\n \n+  iommu-map:\n+    description: |\n+      The mapping of DMA controller channels to IOMMU stream IDs. Each entry in the map specifies the\n+      relationship between a DMA channel and its corresponding IOMMU stream ID. The format is:\n+      \"<ch_no &smmu stream_id length>\". Example: \"<1 &smmu 0x801 1>\"\n+    $ref: /schemas/types.yaml#/definitions/phandle-array\n+\n   dma-coherent: true\n \n   dma-channel-mask:\n","prefixes":["1/8"]}