{"id":2197193,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2197193/?format=json","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.0/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260217-d3cold-v2-4-89b322864043@oss.qualcomm.com>","date":"2026-02-17T11:19:09","name":"[v2,4/5] PCI: qcom: Power down PHY via PARF_PHY_CTRL before disabling rails/clocks","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"d9935285dc18825b6d27b4386b1d9c9c06b334c5","submitter":{"id":89908,"url":"http://patchwork.ozlabs.org/api/1.0/people/89908/?format=json","name":"Krishna Chaitanya Chundru","email":"krishna.chundru@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260217-d3cold-v2-4-89b322864043@oss.qualcomm.com/mbox/","series":[{"id":492410,"url":"http://patchwork.ozlabs.org/api/1.0/series/492410/?format=json","date":"2026-02-17T11:19:05","name":"PCI: qcom: Add D3cold support","version":2,"mbox":"http://patchwork.ozlabs.org/series/492410/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2197193/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=NEL5cgui;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=eFtmxDb7;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260217-d3cold-v2-4-89b322864043@oss.qualcomm.com>","References":"<20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com>","In-Reply-To":"<20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com>","To":"Jingoo Han ,\n Manivannan Sadhasivam ,\n Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= , Rob Herring ,\n Bjorn Helgaas , Will Deacon ","Cc":"linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com,\n Krishna Chaitanya Chundru ","X-Mailer":"b4 0.14.2","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1771327148; l=4007;\n i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id;\n bh=RI4q6fSSubOmDgNNa0gqplTxflnkQiZtd27PDlBbjys=;\n b=li0xu+gi3ab5XV55aDVCdK4EDUgeaa7g/6a4LpfP39jcV9HM2K+TWtxoLN665Lm7JJn/gDR6A\n p55CKSh6k9fAoU1f+ldOyKH3B3W6LSkcx7zyXglg17snwRy2jUfcT+Y","X-Developer-Key":"i=krishna.chundru@oss.qualcomm.com; a=ed25519;\n pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg=","X-Authority-Analysis":"v=2.4 cv=XKo9iAhE c=1 sm=1 tr=0 ts=69944ec4 cx=c_pps\n a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22\n a=EUspDBNiAAAA:8 a=h4B-02p0z56_JbXvspoA:9 a=QEXdDO2ut3YA:10\n a=IoOABgeZipijB_acs4fv:22","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwMjE3MDA5NCBTYWx0ZWRfX8wzrnIoWUM+s\n g19YfzBCEEQgMmCQHNdxE+B/GRWOUhsSVGoUxvHeCfc25zDnEnUsN8DykhRLQ1jZ2GpuSXXMPT5\n vQsOxIGvTa7r0oSMro2JHMQ3epQ2jDCNMcwu7YI0PeReQIxbnD/318tuSpo0vTUMdr3H+2A9pob\n wuEroujU6T6iriJg60onYD/w0etJE8QhFXBXhRZ/iUsUXs1eEqEn5zsvUSlgT0FWS6+Lw8DAsY7\n 58UOVlHi1edHVWfN0+VR0Ju2Aqqhrz8TzxF+hzbOalxLwJqtnAYOK7V96T1ChO+zKmwdaHNQ13x\n 19wQSTLACW+K4583Dgmcw5pFriZkSILZx95ksdiqq3OqNYvTjki75Btau8x86APbIXgqyfLPhBM\n rEeA4UAnXpSyuqYCdVIExyl/mnzpEg7mYiqQ/xqEnn7pftimJcp0VuSiOi+/UkDSWpDsmxdF2NH\n T5qtEFneZGpwEdfA7QQ==","X-Proofpoint-ORIG-GUID":"uaLTS7NP5Jbs7lCih-AexPB-sE0Zjs7C","X-Proofpoint-GUID":"uaLTS7NP5Jbs7lCih-AexPB-sE0Zjs7C","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-02-17_01,2026-02-16_04,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n spamscore=0 phishscore=0 priorityscore=1501 suspectscore=0 bulkscore=0\n clxscore=1015 adultscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602170094"},"content":"Some Qcom PCIe controller variants bring the PHY out of test power-down\n(PHY_TEST_PWR_DOWN) during init. When the link is later transitioned\ntowards D3cold and the driver disables PCIe clocks and/or regulators\nwithout explicitly re-asserting PHY_TEST_PWR_DOWN, the PHY can remain\npartially powered, leading to avoidable power leakage.\n\nUpdate the init-path comments to reflect that PARF_PHY_CTRL is used to\npower the PHY on. Also, for controller revisions that enable PHY power\nin init (2.3.2, 2.3.3, 2.7.0 and 2.9.0), explicitly power the PHY down\nvia PARF_PHY_CTRL in the deinit path before disabling clocks/regulators.\n\nThis ensures the PHY is put into a defined low-power state prior to\nremoving its supplies, preventing leakage when entering D3cold.\n\nSigned-off-by: Krishna Chaitanya Chundru \n---\n drivers/pci/controller/dwc/pcie-qcom.c | 30 +++++++++++++++++++++++++++---\n 1 file changed, 27 insertions(+), 3 deletions(-)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c\nindex 2c4dc7134e006d3530a809f1bcc1a6488d4632ad..b02c19bbdf2ea5db252c2a0281a569bb3a0cc497 100644\n--- a/drivers/pci/controller/dwc/pcie-qcom.c\n+++ b/drivers/pci/controller/dwc/pcie-qcom.c\n@@ -513,7 +513,7 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie)\n \tu32 val;\n \tint ret;\n \n-\t/* enable PCIe clocks and resets */\n+\t/* PHY power ON */\n \tval = readl(pcie->parf + PARF_PHY_CTRL);\n \tval &= ~PHY_TEST_PWR_DOWN;\n \twritel(val, pcie->parf + PARF_PHY_CTRL);\n@@ -680,6 +680,12 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)\n static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)\n {\n \tstruct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;\n+\tu32 val;\n+\n+\t/* PHY Power down */\n+\tval = readl(pcie->parf + PARF_PHY_CTRL);\n+\tval |= PHY_TEST_PWR_DOWN;\n+\twritel(val, pcie->parf + PARF_PHY_CTRL);\n \n \tclk_bulk_disable_unprepare(res->num_clks, res->clks);\n \tregulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);\n@@ -712,7 +718,7 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)\n {\n \tu32 val;\n \n-\t/* enable PCIe clocks and resets */\n+\t/* PHY Power ON */\n \tval = readl(pcie->parf + PARF_PHY_CTRL);\n \tval &= ~PHY_TEST_PWR_DOWN;\n \twritel(val, pcie->parf + PARF_PHY_CTRL);\n@@ -844,6 +850,12 @@ static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)\n static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)\n {\n \tstruct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;\n+\tu32 val;\n+\n+\t/* PHY Power down */\n+\tval = readl(pcie->parf + PARF_PHY_CTRL);\n+\tval |= PHY_TEST_PWR_DOWN;\n+\twritel(val, pcie->parf + PARF_PHY_CTRL);\n \n \tclk_bulk_disable_unprepare(res->num_clks, res->clks);\n }\n@@ -994,7 +1006,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)\n \t/* configure PCIe to RC mode */\n \twritel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);\n \n-\t/* enable PCIe clocks and resets */\n+\t/* PHY power ON */\n \tval = readl(pcie->parf + PARF_PHY_CTRL);\n \tval &= ~PHY_TEST_PWR_DOWN;\n \twritel(val, pcie->parf + PARF_PHY_CTRL);\n@@ -1065,6 +1077,12 @@ static void qcom_pcie_host_post_init_2_7_0(struct qcom_pcie *pcie)\n static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)\n {\n \tstruct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;\n+\tu32 val;\n+\n+\t/* PHY Power down */\n+\tval = readl(pcie->parf + PARF_PHY_CTRL);\n+\tval |= PHY_TEST_PWR_DOWN;\n+\twritel(val, pcie->parf + PARF_PHY_CTRL);\n \n \tclk_bulk_disable_unprepare(res->num_clks, res->clks);\n \n@@ -1169,6 +1187,12 @@ static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)\n static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)\n {\n \tstruct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;\n+\tu32 val;\n+\n+\t/* PHY Power down */\n+\tval = readl(pcie->parf + PARF_PHY_CTRL);\n+\tval |= PHY_TEST_PWR_DOWN;\n+\twritel(val, pcie->parf + PARF_PHY_CTRL);\n \n \tclk_bulk_disable_unprepare(res->num_clks, res->clks);\n }\n","prefixes":["v2","4/5"]}