{"id":2197145,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2197145/?format=json","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.0/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260217080601.3808847-6-den@valinux.co.jp>","date":"2026-02-17T08:05:57","name":"[v8,5/9] PCI: dwc: ep: Expose integrated eDMA resources via EPC aux-resource API","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1df2e352c203fc78432343013686b5536ae10098","submitter":{"id":91573,"url":"http://patchwork.ozlabs.org/api/1.0/people/91573/?format=json","name":"Koichiro Den","email":"den@valinux.co.jp"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260217080601.3808847-6-den@valinux.co.jp/mbox/","series":[{"id":492390,"url":"http://patchwork.ozlabs.org/api/1.0/series/492390/?format=json","date":"2026-02-17T08:05:52","name":"PCI: endpoint: pci-ep-msi: Add embedded doorbell fallback","version":8,"mbox":"http://patchwork.ozlabs.org/series/492390/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2197145/checks/","tags":{},"headers":{"Return-Path":"\n <linux-pci+bounces-47430-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=valinux.co.jp header.i=@valinux.co.jp\n header.a=rsa-sha256 header.s=selector1 header.b=t6DOuzWw;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n 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dkim=pass header.d=valinux.co.jp; arc=none"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=valinux.co.jp;\n s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=3y/7aay/Q1opMjEwmwzIo6Z4aSJnX3go3WXe7OfGjmE=;\n b=t6DOuzWwih0qfdmS0vIdkIPW0UvNwxnur8iMomR5YusO/ZudFFFh1/39PvD4mAr4YRKHL2m/RC/iVQAoj2azme8yb4MAcAn4yF+xm5pHuiXvPPUiTwduMa2KX1e6IbpVx3iP/ia9OG8RTCFwtBxZXTcI0NmU5crT9qcs95cKhgo=","From":"Koichiro Den <den@valinux.co.jp>","To":"jingoohan1@gmail.com,\n\tmani@kernel.org,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\trobh@kernel.org,\n\tbhelgaas@google.com,\n\theiko@sntech.de,\n\tkishon@kernel.org,\n\tjdmason@kudzu.us,\n\tdave.jiang@intel.com,\n\tallenbh@gmail.com,\n\tcassel@kernel.org,\n\tshawn.lin@rock-chips.com,\n\tFrank.Li@nxp.com","Cc":"linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-rockchip@lists.infradead.org,\n\tntb@lists.linux.dev","Subject":"[PATCH v8 5/9] PCI: dwc: ep: Expose integrated eDMA resources via EPC\n aux-resource API","Date":"Tue, 17 Feb 2026 17:05:57 +0900","Message-ID":"<20260217080601.3808847-6-den@valinux.co.jp>","X-Mailer":"git-send-email 2.51.0","In-Reply-To":"<20260217080601.3808847-1-den@valinux.co.jp>","References":"<20260217080601.3808847-1-den@valinux.co.jp>","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"TY4P301CA0116.JPNP301.PROD.OUTLOOK.COM\n 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Ee0W7bNaOmfz9UZX135XPPge+4HKhHwAnWjb/8TMOUZFwrThd2K0LyXRtzbr/JGOAMS0jHwzKc6feoV9csArGIuXRaSZljBM5GEq0njf85JCQ88bk2zYi/5RNxJxGLoU5O9pAu9hS9TMZV1d9wE/S/qHlDlpJ6bBz3zFGXDKQG71ATz7oxBXm/t0ON7gJCUGVHqLq09HbRekdwD6YanAoIKC6usdViFSRsNerorP7wntr4s0xDMF6tOwJbRplNfpjaPw0u+N3Ud35aTW+25Af5asINFMiDdvCp/Tqe84epVLgbN09zW6SzKraxwTXyhpV8ymGz62aHYHGJU/JPQBiv7KnU/HEvZAtbITmnkebd43P9qmKznePD6g7bd9vNeUAk9f8m33EnZp1ZJyz6pzPRrpKaJMWUDx71Qb4o751mJ1qvr4qfcU0LKOSP7V8ICQeg0qVDRlImj0Vfk7Uo3eRSqN2ca2Z+mtBPZEgWJ//tTPV3LL/ClOuz/1kJks/n15XUirZ3KFT1y3G8I93Orq2Nd7d+Zd7A49FueDn3ByFCbshEltJANe61Pr66UuwtVGYKLXV1sXHiufjtl3e1RYb5ZckYR3J6e61D7LE9ePcBTnHVflnwNXamSOTsHQFz2dusJ36qm95OgdfK98XUqdwqGbOuoaAooZvT0cAwe6tzgTISkzJUv3QQFkS3Ssg4yeVCdtAf+dBYb0yH6oqwsZgkj/QOCtRDGxrOHogJDyIX1KR5WRcROblOXyga9/B8Rnvg7jZFEJC7aMSU1VzvGUQyUGvqM4oZ55LBH7eMxO7+1FNiHQoYI0nrrYeegIweNYIdE7eUftwh3JFf8Bqhx6nC3IJhQAkHOaeyLLDkLWvqIDBldSLqLmdd7XeIzkPnEuQRhdhWMc1xTdEWpL0IJ9UxJ+Vt4DUYfr4qjjxB9Awqwm5xAqwGWFrDLeEyRzU1zVN+yFBRPzfnZGupTBeD5DjL2JJekwbNc/abDYmsmk+x0oXCc5GmeMY1Bz7MWZGP2C/FnvB2+9ZHJYrW7n+MGGSR6MCK/hEwoRfbab5pstT/wlEdg7T8ROA22n52Qx/pz2yhCsPtUBrVI0nYXPF8fPeksuSVeXu110noK/4VmWyUuiTYFggqFv7HoG1ziBRy8GXpfDZMErTgZXXhnwHYwxIMixYa+M0y2Ww2cBje4SwzvykHPTlL9AQlPa4Z2QyspGizVIRxnPDBhqZCZjB+L+qZ3v/+eXPmm0zdRHwwRLJS1WcI9tYKIFmngMMXkUdr+U3Nsf6N1c2u7ybps2IouzvEm2S9FvbK4jkWNORNVexcwcXftXOcoPfcXGN56rM861YqEV19Pdhp6OgnOPmm4lZjiBWDX3ufQpmEt+L8gvI0t3vut+BQ/4PJdR6nP6iXW25JdqRyO53uAFDgLAT1Joi9SBHck/VIh7CIRW0yjPJxwwhEgQCivEXOCzPtm5QPsezQ9mjnencUchcWW55Oiq8e14miVT72KCEDzUwisZphN6bEiFGDykP5EYoUnN7Pur/+30nAghapAU80RRa8AZPRABQULwPDVK37d0SWWLb2TvtFi2wsftIlyXuTKaXZaMMGjXpgHcYgNrz1+pL1duUxnZI2pYtGYF7t9myrS0dWhVX6gpSNqMwxr/t8NCxzN3vsO6THKi3tRcNxQHEgnTupXUB2nQxNFAP4+/aRj+TNdMNgndqslHCZ+Syy/Zi4Kwx8A2/q6h3hirNDLcslx8iWSMqx5XNCqcxMPZoQqXoOr6lXqpJgdqF9J+ZsEzC977","X-OriginatorOrg":"valinux.co.jp","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 62545fad-ccb8-4051-1fb5-08de6dfb6a1d","X-MS-Exchange-CrossTenant-AuthSource":"TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"17 Feb 2026 08:06:11.8394\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"7a57bee8-f73d-4c5f-a4f7-d72c91c8c111","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n ghjgU8an8G6AJGBv2fHL8qWY0q1Ng/WWEFMDheY1F6mQgT8MHcp6fosmfXxyuyuhYMiSls31+XvpGmNH/Ws9Wg==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"OS7P286MB7132"},"content":"Implement the EPC aux-resource API for DesignWare endpoint controllers\nwith integrated eDMA.\n\nReport:\n  - DMA controller MMIO window (PCI_EPC_AUX_DMA_CTRL_MMIO)\n  - interrupt-emulation doorbell register (PCI_EPC_AUX_DOORBELL_MMIO),\n    including its Linux IRQ and the data value to write to trigger the\n    interrupt\n  - per-channel LL descriptor regions (PCI_EPC_AUX_DMA_CHAN_DESC)\n\nIf the DMA controller MMIO window is already exposed via a\nplatform-owned fixed BAR subregion, also provide the BAR number and\noffset so EPF drivers can reuse it without reprogramming the BAR.\n\nSigned-off-by: Koichiro Den <den@valinux.co.jp>\n---\nChanges since v7:\n  - Use range_end_overflows_t() instead of an open-coded overflow check.\n  - Make it explicit that the write data is 0 for dw-edma.\n\n .../pci/controller/dwc/pcie-designware-ep.c   | 151 ++++++++++++++++++\n 1 file changed, 151 insertions(+)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c\nindex 7e7844ff0f7e..22b6777d520f 100644\n--- a/drivers/pci/controller/dwc/pcie-designware-ep.c\n+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c\n@@ -9,6 +9,7 @@\n #include <linux/align.h>\n #include <linux/bitfield.h>\n #include <linux/of.h>\n+#include <linux/overflow.h>\n #include <linux/platform_device.h>\n \n #include \"pcie-designware.h\"\n@@ -808,6 +809,155 @@ dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no)\n \treturn ep->ops->get_features(ep);\n }\n \n+static const struct pci_epc_bar_rsvd_region *\n+dw_pcie_ep_find_bar_rsvd_region(struct dw_pcie_ep *ep,\n+\t\t\t\tenum pci_epc_bar_rsvd_region_type type,\n+\t\t\t\tenum pci_barno *bar,\n+\t\t\t\tresource_size_t *bar_offset)\n+{\n+\tconst struct pci_epc_features *features;\n+\tconst struct pci_epc_bar_desc *bar_desc;\n+\tconst struct pci_epc_bar_rsvd_region *r;\n+\tint i, j;\n+\n+\tif (!ep->ops->get_features)\n+\t\treturn NULL;\n+\n+\tfeatures = ep->ops->get_features(ep);\n+\tif (!features)\n+\t\treturn NULL;\n+\n+\tfor (i = BAR_0; i <= BAR_5; i++) {\n+\t\tbar_desc = &features->bar[i];\n+\n+\t\tif (!bar_desc->nr_rsvd_regions || !bar_desc->rsvd_regions)\n+\t\t\tcontinue;\n+\n+\t\tfor (j = 0; j < bar_desc->nr_rsvd_regions; j++) {\n+\t\t\tr = &bar_desc->rsvd_regions[j];\n+\n+\t\t\tif (r->type != type)\n+\t\t\t\tcontinue;\n+\n+\t\t\tif (bar)\n+\t\t\t\t*bar = i;\n+\t\t\tif (bar_offset)\n+\t\t\t\t*bar_offset = r->offset;\n+\t\t\treturn r;\n+\t\t}\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static int\n+dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 func_no, u8 vfunc_no,\n+\t\t\t     struct pci_epc_aux_resource *resources,\n+\t\t\t     int num_resources)\n+{\n+\tstruct dw_pcie_ep *ep = epc_get_drvdata(epc);\n+\tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n+\tconst struct pci_epc_bar_rsvd_region *rsvd;\n+\tstruct dw_edma_chip *edma = &pci->edma;\n+\tenum pci_barno dma_ctrl_bar = NO_BAR;\n+\tint ll_cnt = 0, needed, idx = 0;\n+\tresource_size_t db_offset = edma->db_offset;\n+\tresource_size_t dma_ctrl_bar_offset = 0;\n+\tresource_size_t dma_reg_size;\n+\tunsigned int i;\n+\n+\tif (!pci->edma_reg_size)\n+\t\treturn 0;\n+\n+\tdma_reg_size = pci->edma_reg_size;\n+\n+\tfor (i = 0; i < edma->ll_wr_cnt; i++)\n+\t\tif (edma->ll_region_wr[i].sz)\n+\t\t\tll_cnt++;\n+\n+\tfor (i = 0; i < edma->ll_rd_cnt; i++)\n+\t\tif (edma->ll_region_rd[i].sz)\n+\t\t\tll_cnt++;\n+\n+\tneeded = 1 + ll_cnt + (db_offset != ~0 ? 1 : 0);\n+\n+\t/* Count query mode */\n+\tif (!resources || !num_resources)\n+\t\treturn needed;\n+\n+\tif (num_resources < needed)\n+\t\treturn -ENOSPC;\n+\n+\trsvd = dw_pcie_ep_find_bar_rsvd_region(ep,\n+\t\t\t\t\t       PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO,\n+\t\t\t\t\t       &dma_ctrl_bar,\n+\t\t\t\t\t       &dma_ctrl_bar_offset);\n+\tif (rsvd && rsvd->size < dma_reg_size)\n+\t\tdma_reg_size = rsvd->size;\n+\n+\t/* DMA register block */\n+\tresources[idx++] = (struct pci_epc_aux_resource) {\n+\t\t.type = PCI_EPC_AUX_DMA_CTRL_MMIO,\n+\t\t.phys_addr = pci->edma_reg_phys,\n+\t\t.size = dma_reg_size,\n+\t\t.bar = dma_ctrl_bar,\n+\t\t.bar_offset = dma_ctrl_bar_offset,\n+\t};\n+\n+\t/*\n+\t * For interrupt-emulation doorbells, report a standalone resource\n+\t * instead of bundling it into the DMA controller MMIO resource.\n+\t */\n+\tif (db_offset != ~0) {\n+\t\tif (range_end_overflows_t(resource_size_t, db_offset,\n+\t\t\t\t\t  sizeof(u32), dma_reg_size))\n+\t\t\treturn -EINVAL;\n+\n+\t\tresources[idx++] = (struct pci_epc_aux_resource) {\n+\t\t\t.type = PCI_EPC_AUX_DOORBELL_MMIO,\n+\t\t\t.phys_addr = pci->edma_reg_phys + db_offset,\n+\t\t\t.size = sizeof(u32),\n+\t\t\t.bar = dma_ctrl_bar,\n+\t\t\t.bar_offset = dma_ctrl_bar != NO_BAR ?\n+\t\t\t\t\tdma_ctrl_bar_offset + db_offset : 0,\n+\t\t\t.u.db_mmio = {\n+\t\t\t\t.irq = edma->db_irq,\n+\t\t\t\t.data = 0, /* write 0 to assert */\n+\t\t\t},\n+\t\t};\n+\t}\n+\n+\t/* One LL region per write channel */\n+\tfor (i = 0; i < edma->ll_wr_cnt; i++) {\n+\t\tif (!edma->ll_region_wr[i].sz)\n+\t\t\tcontinue;\n+\n+\t\tresources[idx++] = (struct pci_epc_aux_resource) {\n+\t\t\t.type = PCI_EPC_AUX_DMA_CHAN_DESC,\n+\t\t\t.phys_addr = edma->ll_region_wr[i].paddr,\n+\t\t\t.size = edma->ll_region_wr[i].sz,\n+\t\t\t.bar = NO_BAR,\n+\t\t\t.bar_offset = 0,\n+\t\t};\n+\t}\n+\n+\t/* One LL region per read channel */\n+\tfor (i = 0; i < edma->ll_rd_cnt; i++) {\n+\t\tif (!edma->ll_region_rd[i].sz)\n+\t\t\tcontinue;\n+\n+\t\tresources[idx++] = (struct pci_epc_aux_resource) {\n+\t\t\t.type = PCI_EPC_AUX_DMA_CHAN_DESC,\n+\t\t\t.phys_addr = edma->ll_region_rd[i].paddr,\n+\t\t\t.size = edma->ll_region_rd[i].sz,\n+\t\t\t.bar = NO_BAR,\n+\t\t\t.bar_offset = 0,\n+\t\t};\n+\t}\n+\n+\treturn idx;\n+}\n+\n static const struct pci_epc_ops epc_ops = {\n \t.write_header\t\t= dw_pcie_ep_write_header,\n \t.set_bar\t\t= dw_pcie_ep_set_bar,\n@@ -823,6 +973,7 @@ static const struct pci_epc_ops epc_ops = {\n \t.start\t\t\t= dw_pcie_ep_start,\n \t.stop\t\t\t= dw_pcie_ep_stop,\n \t.get_features\t\t= dw_pcie_ep_get_features,\n+\t.get_aux_resources\t= dw_pcie_ep_get_aux_resources,\n };\n \n /**\n","prefixes":["v8","5/9"]}