{"id":2197136,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2197136/?format=json","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.0/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260217080102.206581-4-sunlightlinux@gmail.com>","date":"2026-02-17T08:00:58","name":"[RFC,1/3] PCI: Add PCIe Gen 7 (128 GT/s) register and speed definitions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"25fd49bb180da080a97a565a2f194a74b32adf1a","submitter":{"id":92653,"url":"http://patchwork.ozlabs.org/api/1.0/people/92653/?format=json","name":"Ionut Nechita (Sunlight Linux)","email":"sunlightlinux@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260217080102.206581-4-sunlightlinux@gmail.com/mbox/","series":[{"id":492389,"url":"http://patchwork.ozlabs.org/api/1.0/series/492389/?format=json","date":"2026-02-17T08:00:56","name":"PCI: Add PCIe Gen 7 (128 GT/s) speed support","version":1,"mbox":"http://patchwork.ozlabs.org/series/492389/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2197136/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=ZU/pKziZ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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Wysocki\" ,\n Daniel Lezcano ","Cc":"Zhang Rui ,\n\tLukasz Luba ,\n\tLukas Wunner ,\n\tIonut Nechita ,\n\tlinux-pci@vger.kernel.org,\n\tlinux-pm@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tIonut Nechita ","Subject":"[RFC PATCH 1/3] PCI: Add PCIe Gen 7 (128 GT/s) register and speed\n definitions","Date":"Tue, 17 Feb 2026 10:00:58 +0200","Message-ID":"<20260217080102.206581-4-sunlightlinux@gmail.com>","X-Mailer":"git-send-email 2.53.0","In-Reply-To":"<20260217080102.206581-2-sunlightlinux@gmail.com>","References":"<20260217080102.206581-2-sunlightlinux@gmail.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit"},"content":"From: Ionut Nechita \n\nAdd register definitions for PCIe Gen 7 128 GT/s link speed:\n\n - PCI_EXP_LNKCAP_SLS_128_0GB (encoding 0x7)\n - PCI_EXP_LNKCAP2_SLS_128_0GB (bit 6 in Supported Link Speeds Vector)\n - PCI_EXP_LNKCTL2_TLS_128_0GT (Target Link Speed 0x7)\n - PCIE_SPEED_128_0GT enum value (0x1a)\n\nWiden pci_dev.supported_speeds from u8 to u16 to accommodate the\nexpanded Supported Link Speeds Vector which now uses bits 1-7.\n\nPCIe Gen 7 doubles the data rate to 128 GT/s using PAM4 signaling\nwith mandatory Flit mode encoding (1:1, no overhead), providing\nup to 256 GB/s unidirectional (512 GB/s bi-directional) bandwidth\non an x16 link.\n\nNote: Based on the PCIe 7.0 specification announced by PCI-SIG in\n2022, targeted for member release in 2025. No hardware exists yet\nto validate these definitions.\n\nSigned-off-by: Ionut Nechita \n---\n include/linux/pci.h | 3 ++-\n include/uapi/linux/pci_regs.h | 3 +++\n 2 files changed, 5 insertions(+), 1 deletion(-)","diff":"diff --git a/include/linux/pci.h b/include/linux/pci.h\nindex b5cc0c2b99065..21dd6ea5beb6d 100644\n--- a/include/linux/pci.h\n+++ b/include/linux/pci.h\n@@ -303,6 +303,7 @@ enum pci_bus_speed {\n \tPCIE_SPEED_16_0GT\t\t= 0x17,\n \tPCIE_SPEED_32_0GT\t\t= 0x18,\n \tPCIE_SPEED_64_0GT\t\t= 0x19,\n+\tPCIE_SPEED_128_0GT\t\t= 0x1a,\n \tPCI_SPEED_UNKNOWN\t\t= 0xff,\n };\n \n@@ -558,7 +559,7 @@ struct pci_dev {\n \tstruct pci_tsm *tsm;\t\t/* TSM operation state */\n #endif\n \tu16\t\tacs_cap;\t/* ACS Capability offset */\n-\tu8\t\tsupported_speeds; /* Supported Link Speeds Vector */\n+\tu16\t\tsupported_speeds; /* Supported Link Speeds Vector */\n \tphys_addr_t\trom;\t\t/* Physical address if not from BAR */\n \tsize_t\t\tromlen;\t\t/* Length if not from BAR */\n \t/*\ndiff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h\nindex 3add74ae25948..fa00c6ca9f382 100644\n--- a/include/uapi/linux/pci_regs.h\n+++ b/include/uapi/linux/pci_regs.h\n@@ -545,6 +545,7 @@\n #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */\n #define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */\n #define PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */\n+#define PCI_EXP_LNKCAP_SLS_128_0GB 0x00000007 /* LNKCAP2 SLS Vector bit 6 */\n #define PCI_EXP_LNKCAP_MLW\t0x000003f0 /* Maximum Link Width */\n #define PCI_EXP_LNKCAP_ASPMS\t0x00000c00 /* ASPM Support */\n #define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */\n@@ -693,6 +694,7 @@\n #define PCI_EXP_LNKCAP2_SLS_16_0GB\t0x00000010 /* Supported Speed 16GT/s */\n #define PCI_EXP_LNKCAP2_SLS_32_0GB\t0x00000020 /* Supported Speed 32GT/s */\n #define PCI_EXP_LNKCAP2_SLS_64_0GB\t0x00000040 /* Supported Speed 64GT/s */\n+#define PCI_EXP_LNKCAP2_SLS_128_0GB\t0x00000080 /* Supported Speed 128GT/s */\n #define PCI_EXP_LNKCAP2_CROSSLINK\t0x00000100 /* Crosslink supported */\n #define PCI_EXP_LNKCTL2\t\t0x30\t/* Link Control 2 */\n #define PCI_EXP_LNKCTL2_TLS\t\t0x000f\n@@ -702,6 +704,7 @@\n #define PCI_EXP_LNKCTL2_TLS_16_0GT\t0x0004 /* Supported Speed 16GT/s */\n #define PCI_EXP_LNKCTL2_TLS_32_0GT\t0x0005 /* Supported Speed 32GT/s */\n #define PCI_EXP_LNKCTL2_TLS_64_0GT\t0x0006 /* Supported Speed 64GT/s */\n+#define PCI_EXP_LNKCTL2_TLS_128_0GT\t0x0007 /* Supported Speed 128GT/s */\n #define PCI_EXP_LNKCTL2_ENTER_COMP\t0x0010 /* Enter Compliance */\n #define PCI_EXP_LNKCTL2_TX_MARGIN\t0x0380 /* Transmit Margin */\n #define PCI_EXP_LNKCTL2_HASD\t\t0x0020 /* HW Autonomous Speed Disable */\n","prefixes":["RFC","1/3"]}