{"id":2196695,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2196695/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260216034432.23912-13-richard.henderson@linaro.org>","date":"2026-02-16T03:44:31","name":"[RFC,12/13] target/arm: Add SME state to kvm_arch_{get, put}_registers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e6bbfc0a39078f2843ec455ead0aef87dee708b1","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.0/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260216034432.23912-13-richard.henderson@linaro.org/mbox/","series":[{"id":492243,"url":"http://patchwork.ozlabs.org/api/1.0/series/492243/?format=json","date":"2026-02-16T03:44:19","name":"target/arm: Support SME for KVM","version":1,"mbox":"http://patchwork.ozlabs.org/series/492243/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2196695/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=QD8H0kCA;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fDpbf2P8Xz1xxp\n\tfor ; Mon, 16 Feb 2026 14:46:22 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1vrpXs-0002hm-SJ; Sun, 15 Feb 2026 22:45:12 -0500","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1vrpXn-0002de-Qt\n for qemu-devel@nongnu.org; Sun, 15 Feb 2026 22:45:07 -0500","from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1vrpXl-0002T8-3Z\n for qemu-devel@nongnu.org; Sun, 15 Feb 2026 22:45:07 -0500","by mail-pl1-x632.google.com with SMTP id\n d9443c01a7336-2a7a9b8ed69so27641535ad.2\n for ; Sun, 15 Feb 2026 19:45:03 -0800 (PST)","from stoup.. ([2401:d002:dc0f:2100:4a1:428a:70f2:5844])\n by smtp.gmail.com with ESMTPSA id\n d9443c01a7336-2ad1aadca84sm53294155ad.70.2026.02.15.19.45.01\n for \n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Sun, 15 Feb 2026 19:45:02 -0800 (PST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1771213503; x=1771818303; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:from:to:cc:subject:date:message-id\n :reply-to; bh=oeZjdzqdE1iuyBszq/Z//al5shVLI8GhqttWbbZVCxI=;\n b=QD8H0kCA+7qH+w3USdDjw8+EmP2a1g7vpmfyASliStMJBvGoxd9fjyW7WdMrTwwvs9\n +AAisdpYdUM23j/pTzk5XuvT5ulFJHHAFcBkrIg6kyqMS33xQ6vueLqaVIWnCGqLG6z6\n +fnPTn/liNHoFXKq1gBeI78Wm4+r+6e7+t8D0xcyfhCxPQ90qK14eG7wK9LsBsq2pS0m\n sWrMZNg6woO/5spL8nhaeH15F71G1LX/uKdJ2x63/QV7Nc4avh316OsPeWmt35gkAXa+\n hpFA6lauCQacqEgKNZuOPWcB5tQr92sp3DqQP3m8ksnJp0mJS+XB+5/7+953qcRZauRN\n q0jg==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1771213503; x=1771818303;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=oeZjdzqdE1iuyBszq/Z//al5shVLI8GhqttWbbZVCxI=;\n b=WwKhIoyg6gmmR+jGAO7jKYLQj6SPC+3BEvlR37qgjWO6Z3liYlZJ0Ceaal0pt5366v\n ZV/o09s08kJgrNkTetfT41xUK6DWPybRSdOxpJHszotVRihPdasm59hRGoXDgFTh7aIY\n 9/O8qkxAnXNW6TdaNV+ZNMy0LhklKCD0RODoYnklv5vFgWHx9BgwHpUcwcR8TpDgxZrQ\n Hxxxy4OSey2FzOrtTelGHRoGRry1hGDsOt2rX9YRoPhRIxcG2IA+Fmb2BPHwVYxV4lQp\n RIhez96bSG2hYAac07Kmhxm3rZt5vDOhVP5JMCqoNpeE06rFUrzAXF6g8iFCKvNCpZko\n LLoQ==","X-Gm-Message-State":"AOJu0YyJiO5XSXAWDxHyrhpRqEUAWqgdj5RTVh8bCAn0f/kHafefv0ed\n oKyPaGikyFFjAm5A+UP7o4HnnnRFWGhPdCb983Pf+t/wzysyZQv9YG0csroVhSdF5wXsJmVAIru\n SD2ZrDFY=","X-Gm-Gg":"AZuq6aJNh1brwaSxBFSLHpCkhfAy4Q34869xXiOOLp29/aOw4y/Suty1z2Hc/0tdvZY\n 3LvoyBGALnIUxCSfL6DTQRTtcCFBqDRP1U/RQC1nrDEoiMXBGYbs9La0jsUPqjgATKxJQaQGoOd\n uJ0hyd7M5MDcY1pvhOZBIDBo0Qk2r2DA4SnBo0HIGBqVKD8QlYrBb6mlaSguXhGtKXr+z6mAyPz\n QydjQA4r0QV3Ax5/IlTGyAzjPy+A4xj3Fr3UqlXyRbKOAnHursyUFrCrVqCQMBFtWBT+Qq/tEH8\n pi51zJ1qmXwORTRjaX38m3sJ0Lr01hxhJhY6zB98lDKDrTBH2ephtReB8X/gjYurAuwwfv5wESi\n uMpJId0TF9xjKdnNa5f/f/ZOO5ffMaOqGNhO77RxeONpRPttKpqUTfhcakDUZ5RC2oM7LpSzG2y\n T8rik6CVbh4LnL4R8bYCMjzk089AEDLELl","X-Received":"by 2002:a17:902:e787:b0:2aa:d11d:5c36 with SMTP id\n d9443c01a7336-2ab50598a38mr96753725ad.30.1771213502651;\n Sun, 15 Feb 2026 19:45:02 -0800 (PST)","From":"Richard Henderson ","To":"qemu-devel@nongnu.org","Subject":"[RFC PATCH 12/13] target/arm: Add SME state to kvm_arch_{get,\n put}_registers","Date":"Mon, 16 Feb 2026 13:44:31 +1000","Message-ID":"<20260216034432.23912-13-richard.henderson@linaro.org>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260216034432.23912-1-richard.henderson@linaro.org>","References":"<20260216034432.23912-1-richard.henderson@linaro.org>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::632;\n envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/kvm.c | 104 ++++++++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 102 insertions(+), 2 deletions(-)","diff":"diff --git a/target/arm/kvm.c b/target/arm/kvm.c\nindex d05ad1d7e1..6d849573be 100644\n--- a/target/arm/kvm.c\n+++ b/target/arm/kvm.c\n@@ -43,6 +43,11 @@\n #include \"target/arm/gtimer.h\"\n #include \"migration/blocker.h\"\n \n+/* ??? This probably belongs in asm-arm64/kvm.h */\n+#define KVM_REG_ARM64_SME_ZT0 \\\n+ (KVM_REG_ARM64 | KVM_REG_ARM64_SME | \\\n+ KVM_REG_ARM64_SME_ZT_BASE | KVM_REG_SIZE_U512)\n+\n const KVMCapabilityInfo kvm_arch_required_capabilities[] = {\n KVM_CAP_INFO(DEVICE_CTRL),\n KVM_CAP_LAST_INFO\n@@ -2157,10 +2162,39 @@ static int kvm_arch_put_sve(CPUState *cs, uint32_t vq, bool have_ffr)\n return 0;\n }\n \n+static int kvm_arch_put_sme(CPUState *cs, uint32_t svq)\n+{\n+ CPUARMState *env = cpu_env(cs);\n+ ARMCPU *cpu = env_archcpu(env);\n+ uint64_t tmp[ARM_MAX_VQ * 2];\n+ uint64_t *r;\n+ int ret;\n+\n+ for (int n = 0; n < svq * 16; ++n) {\n+ r = sve_bswap64(tmp, &env->za_state.za[n].d[0], svq * 2);\n+ ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SME_ZAHREG(n, 0), r);\n+ if (ret) {\n+ return ret;\n+ }\n+ }\n+\n+ if (cpu_isar_feature(aa64_sme2, cpu)) {\n+ r = sve_bswap64(tmp, env->za_state.zt0, ARRAY_SIZE(env->za_state.zt0));\n+ ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SME_ZT0, r);\n+ if (ret) {\n+ return ret;\n+ }\n+ }\n+ return 0;\n+}\n+\n int kvm_arch_put_registers(CPUState *cs, KvmPutState level, Error **errp)\n {\n uint64_t val;\n uint32_t fpr;\n+ bool sme_sm = false;\n+ bool sme_za = false;\n+ uint32_t svq = 0;\n int i, ret;\n unsigned int el;\n \n@@ -2239,7 +2273,18 @@ int kvm_arch_put_registers(CPUState *cs, KvmPutState level, Error **errp)\n }\n }\n \n- if (cpu_isar_feature(aa64_sve, cpu)) {\n+ if (cpu_isar_feature(aa64_sme, cpu)) {\n+ /* Current SVL is required for either SM or ZA */\n+ sme_sm = FIELD_EX64(env->svcr, SVCR, SM);\n+ sme_za = FIELD_EX64(env->svcr, SVCR, ZA);\n+ if (sme_sm || sme_za) {\n+ svq = sve_vqm1_for_el_sm(env, el, true) + 1;\n+ }\n+ }\n+\n+ if (sme_sm) {\n+ ret = kvm_arch_put_sve(cs, svq, cpu_isar_feature(aa64_sme_fa64, cpu));\n+ } else if (cpu_isar_feature(aa64_sve, cpu)) {\n ret = kvm_arch_put_sve(cs, cpu->sve_max_vq, true);\n } else {\n ret = kvm_arch_put_fpsimd(cs);\n@@ -2248,6 +2293,13 @@ int kvm_arch_put_registers(CPUState *cs, KvmPutState level, Error **errp)\n return ret;\n }\n \n+ if (sme_za) {\n+ ret = kvm_arch_put_sme(cs, svq);\n+ if (ret) {\n+ return ret;\n+ }\n+ }\n+\n fpr = vfp_get_fpsr(env);\n ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr);\n if (ret) {\n@@ -2342,11 +2394,41 @@ static int kvm_arch_get_sve(CPUState *cs, uint32_t vq, bool have_ffr)\n return 0;\n }\n \n+static int kvm_arch_get_sme(CPUState *cs, uint32_t svq)\n+{\n+ CPUARMState *env = cpu_env(cs);\n+ ARMCPU *cpu = env_archcpu(env);\n+ uint64_t *r;\n+ int ret;\n+\n+ for (int n = 0; n < svq * 16; ++n) {\n+ r = &env->za_state.za[n].d[0];\n+ ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SME_ZAHREG(n, 0), r);\n+ if (ret) {\n+ return ret;\n+ }\n+ sve_bswap64(r, r, svq * 2);\n+ }\n+\n+ if (cpu_isar_feature(aa64_sme2, cpu)) {\n+ r = env->za_state.zt0;\n+ ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SME_ZT0, r);\n+ if (ret) {\n+ return ret;\n+ }\n+ sve_bswap64(r, r, ARRAY_SIZE(env->za_state.zt0));\n+ }\n+ return 0;\n+}\n+\n int kvm_arch_get_registers(CPUState *cs, Error **errp)\n {\n uint64_t val;\n unsigned int el;\n uint32_t fpr;\n+ bool sme_sm = false;\n+ bool sme_za = false;\n+ uint32_t svq = 0;\n int i, ret;\n \n ARMCPU *cpu = ARM_CPU(cs);\n@@ -2424,7 +2506,18 @@ int kvm_arch_get_registers(CPUState *cs, Error **errp)\n env->spsr = env->banked_spsr[i];\n }\n \n- if (cpu_isar_feature(aa64_sve, cpu)) {\n+ if (cpu_isar_feature(aa64_sme, cpu)) {\n+ /* Current SVL is required for either SM or ZA */\n+ sme_sm = FIELD_EX64(env->svcr, SVCR, SM);\n+ sme_za = FIELD_EX64(env->svcr, SVCR, ZA);\n+ if (sme_sm || sme_za) {\n+ svq = sve_vqm1_for_el_sm(env, el, true) + 1;\n+ }\n+ }\n+\n+ if (sme_sm) {\n+ ret = kvm_arch_get_sve(cs, svq, cpu_isar_feature(aa64_sme_fa64, cpu));\n+ } else if (cpu_isar_feature(aa64_sve, cpu)) {\n ret = kvm_arch_get_sve(cs, cpu->sve_max_vq, true);\n } else {\n ret = kvm_arch_get_fpsimd(cs);\n@@ -2433,6 +2526,13 @@ int kvm_arch_get_registers(CPUState *cs, Error **errp)\n return ret;\n }\n \n+ if (sme_za) {\n+ ret = kvm_arch_get_sme(cs, svq);\n+ if (ret) {\n+ return ret;\n+ }\n+ }\n+\n ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr);\n if (ret) {\n return ret;\n","prefixes":["RFC","12/13"]}