{"id":2196694,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2196694/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260216034432.23912-6-richard.henderson@linaro.org>","date":"2026-02-16T03:44:24","name":"[RFC,05/13] target/arm: Move kvm test out of cpu_arm_set_sve","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"28e4bb9185ced71bfc4b43c4c901b58f4b30c7ed","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.0/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260216034432.23912-6-richard.henderson@linaro.org/mbox/","series":[{"id":492243,"url":"http://patchwork.ozlabs.org/api/1.0/series/492243/?format=json","date":"2026-02-16T03:44:19","name":"target/arm: Support SME for KVM","version":1,"mbox":"http://patchwork.ozlabs.org/series/492243/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2196694/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=a5BATFP0;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fDpbf0ltmz1xpl\n\tfor ; Mon, 16 Feb 2026 14:46:22 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1vrpXZ-0002XM-A7; Sun, 15 Feb 2026 22:44:53 -0500","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1vrpXX-0002Wr-Q0\n for qemu-devel@nongnu.org; Sun, 15 Feb 2026 22:44:51 -0500","from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1vrpXW-0002QU-Ac\n for qemu-devel@nongnu.org; Sun, 15 Feb 2026 22:44:51 -0500","by mail-pl1-x62b.google.com with SMTP id\n d9443c01a7336-2a9296b3926so17971075ad.1\n for ; Sun, 15 Feb 2026 19:44:49 -0800 (PST)","from stoup.. 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Register the real or stub\nfuntions in aarch64_add_sve_properties depending on whether or\nnot SVE is available.\n\nAdjust aarch64_a64fx_initfn to initialize the set of supported\nvector sizes before calling aarch64_add_sve_properties.\n\nSigned-off-by: Richard Henderson \n---\n target/arm/cpu64.c | 48 ++++++++++++++++++++++++++++++++++++------\n target/arm/tcg/cpu64.c | 2 +-\n 2 files changed, 42 insertions(+), 8 deletions(-)","diff":"diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c\nindex 0116b6cc88..38d06af49f 100644\n--- a/target/arm/cpu64.c\n+++ b/target/arm/cpu64.c\n@@ -292,6 +292,30 @@ static void cpu_arm_set_vq(Object *obj, Visitor *v, const char *name,\n vq_map->init |= 1 << (vq - 1);\n }\n \n+static void prop_bool_get_false(Object *obj, Visitor *v, const char *name,\n+ void *opaque, Error **errp)\n+{\n+ bool value = false;\n+ visit_type_bool(v, name, &value, errp);\n+}\n+\n+static void prop_bool_set_false(Object *obj, Visitor *v, const char *name,\n+ void *opaque, Error **errp)\n+{\n+ bool value;\n+\n+ if (visit_type_bool(v, name, &value, errp) && value) {\n+ error_setg(errp, \"'%s' feature not supported by %s on this host\",\n+ name, current_accel_name());\n+ }\n+}\n+\n+static void prop_add_stub_bool(Object *obj, const char *name)\n+{\n+ object_property_add(obj, name, \"bool\", prop_bool_get_false,\n+ prop_bool_set_false, NULL, NULL);\n+}\n+\n static bool cpu_arm_get_sve(Object *obj, Error **errp)\n {\n ARMCPU *cpu = ARM_CPU(obj);\n@@ -301,12 +325,6 @@ static bool cpu_arm_get_sve(Object *obj, Error **errp)\n static void cpu_arm_set_sve(Object *obj, bool value, Error **errp)\n {\n ARMCPU *cpu = ARM_CPU(obj);\n-\n- if (value && kvm_enabled() && !kvm_arm_sve_supported()) {\n- error_setg(errp, \"'sve' feature not supported by KVM on this host\");\n- return;\n- }\n-\n FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, SVE, value);\n }\n \n@@ -439,7 +457,23 @@ void aarch64_add_sve_properties(Object *obj)\n ARMCPU *cpu = ARM_CPU(obj);\n uint32_t vq;\n \n- object_property_add_bool(obj, \"sve\", cpu_arm_get_sve, cpu_arm_set_sve);\n+ /*\n+ * For hw virtualization, we have already probed the set of vector\n+ * lengths supported. If there are none, the host doesn't support\n+ * SVE at all. In which case we register a stub property, to allow\n+ * -cpu max,sve=off\n+ * to always be valid.\n+ *\n+ * For TCG, this function is only called for cpu models which\n+ * support SVE. The error message in the stub is written\n+ * assuming host virtualiation is being used.\n+ */\n+ if (cpu->sve_vq.supported) {\n+ object_property_add_bool(obj, \"sve\", cpu_arm_get_sve, cpu_arm_set_sve);\n+ } else {\n+ assert(!tcg_enabled());\n+ prop_add_stub_bool(obj, \"sve\");\n+ }\n \n for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {\n char name[8];\ndiff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c\nindex fa80e48d2b..84857fb706 100644\n--- a/target/arm/tcg/cpu64.c\n+++ b/target/arm/tcg/cpu64.c\n@@ -524,10 +524,10 @@ static void aarch64_a64fx_initfn(Object *obj)\n cpu->gic_pribits = 5;\n \n /* The A64FX supports only 128, 256 and 512 bit vector lengths */\n- aarch64_add_sve_properties(obj);\n cpu->sve_vq.supported = (1 << 0) /* 128bit */\n | (1 << 1) /* 256bit */\n | (1 << 3); /* 512bit */\n+ aarch64_add_sve_properties(obj);\n \n cpu->isar.reset_pmcr_el0 = 0x46014040;\n \n","prefixes":["RFC","05/13"]}