{"id":2196693,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2196693/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260216034432.23912-11-richard.henderson@linaro.org>","date":"2026-02-16T03:44:29","name":"[RFC,10/13] target/arm: Add vq argument to kvm_arch_{get, put}_sve","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"7145482375f6012a8d35da87accb00b4e91e1040","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.0/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260216034432.23912-11-richard.henderson@linaro.org/mbox/","series":[{"id":492243,"url":"http://patchwork.ozlabs.org/api/1.0/series/492243/?format=json","date":"2026-02-16T03:44:19","name":"target/arm: Support SME for KVM","version":1,"mbox":"http://patchwork.ozlabs.org/series/492243/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2196693/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=CoHzRVqH;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fDpbb741nz1xxp\n\tfor ; Mon, 16 Feb 2026 14:46:19 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1vrpXl-0002d2-UJ; Sun, 15 Feb 2026 22:45:05 -0500","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1vrpXk-0002bd-0y\n for qemu-devel@nongnu.org; Sun, 15 Feb 2026 22:45:04 -0500","from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1vrpXg-0002SR-68\n for qemu-devel@nongnu.org; Sun, 15 Feb 2026 22:45:03 -0500","by mail-pl1-x62a.google.com with SMTP id\n d9443c01a7336-2a9296b3926so17971705ad.1\n for ; Sun, 15 Feb 2026 19:44:59 -0800 (PST)","from stoup.. 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helo=mail-pl1-x62a.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/kvm.c | 27 ++++++++++++---------------\n 1 file changed, 12 insertions(+), 15 deletions(-)","diff":"diff --git a/target/arm/kvm.c b/target/arm/kvm.c\nindex 979265a810..f6bab562a0 100644\n--- a/target/arm/kvm.c\n+++ b/target/arm/kvm.c\n@@ -2122,16 +2122,15 @@ static int kvm_arch_put_fpsimd(CPUState *cs)\n * code the slice index to zero for now as it's unlikely we'll need more than\n * one slice for quite some time.\n */\n-static int kvm_arch_put_sve(CPUState *cs)\n+static int kvm_arch_put_sve(CPUState *cs, uint32_t vq)\n {\n- ARMCPU *cpu = ARM_CPU(cs);\n- CPUARMState *env = &cpu->env;\n+ CPUARMState *env = cpu_env(cs);\n uint64_t tmp[ARM_MAX_VQ * 2];\n uint64_t *r;\n int n, ret;\n \n for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {\n- r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2);\n+ r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], vq * 2);\n ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r);\n if (ret) {\n return ret;\n@@ -2139,8 +2138,7 @@ static int kvm_arch_put_sve(CPUState *cs)\n }\n \n for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {\n- r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0],\n- DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));\n+ r = sve_bswap64(tmp, &env->vfp.pregs[n].p[0], DIV_ROUND_UP(vq * 2, 8));\n ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r);\n if (ret) {\n return ret;\n@@ -2148,7 +2146,7 @@ static int kvm_arch_put_sve(CPUState *cs)\n }\n \n r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0],\n- DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));\n+ DIV_ROUND_UP(vq * 2, 8));\n ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r);\n if (ret) {\n return ret;\n@@ -2240,7 +2238,7 @@ int kvm_arch_put_registers(CPUState *cs, KvmPutState level, Error **errp)\n }\n \n if (cpu_isar_feature(aa64_sve, cpu)) {\n- ret = kvm_arch_put_sve(cs);\n+ ret = kvm_arch_put_sve(cs, cpu->sve_max_vq);\n } else {\n ret = kvm_arch_put_fpsimd(cs);\n }\n@@ -2306,10 +2304,9 @@ static int kvm_arch_get_fpsimd(CPUState *cs)\n * code the slice index to zero for now as it's unlikely we'll need more than\n * one slice for quite some time.\n */\n-static int kvm_arch_get_sve(CPUState *cs)\n+static int kvm_arch_get_sve(CPUState *cs, uint32_t vq)\n {\n- ARMCPU *cpu = ARM_CPU(cs);\n- CPUARMState *env = &cpu->env;\n+ CPUARMState *env = cpu_env(cs);\n uint64_t *r;\n int n, ret;\n \n@@ -2319,7 +2316,7 @@ static int kvm_arch_get_sve(CPUState *cs)\n if (ret) {\n return ret;\n }\n- sve_bswap64(r, r, cpu->sve_max_vq * 2);\n+ sve_bswap64(r, r, vq * 2);\n }\n \n for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {\n@@ -2328,7 +2325,7 @@ static int kvm_arch_get_sve(CPUState *cs)\n if (ret) {\n return ret;\n }\n- sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));\n+ sve_bswap64(r, r, DIV_ROUND_UP(vq * 2, 8));\n }\n \n r = &env->vfp.pregs[FFR_PRED_NUM].p[0];\n@@ -2336,7 +2333,7 @@ static int kvm_arch_get_sve(CPUState *cs)\n if (ret) {\n return ret;\n }\n- sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));\n+ sve_bswap64(r, r, DIV_ROUND_UP(vq * 2, 8));\n \n return 0;\n }\n@@ -2424,7 +2421,7 @@ int kvm_arch_get_registers(CPUState *cs, Error **errp)\n }\n \n if (cpu_isar_feature(aa64_sve, cpu)) {\n- ret = kvm_arch_get_sve(cs);\n+ ret = kvm_arch_get_sve(cs, cpu->sve_max_vq);\n } else {\n ret = kvm_arch_get_fpsimd(cs);\n }\n","prefixes":["RFC","10/13"]}