{"id":2196692,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2196692/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260216034432.23912-14-richard.henderson@linaro.org>","date":"2026-02-16T03:44:32","name":"[RFC,13/13] target/arm: Add SME properties for KVM","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0d3b3cf0460cd52c270140e69ef7eecdf62d5634","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.0/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260216034432.23912-14-richard.henderson@linaro.org/mbox/","series":[{"id":492243,"url":"http://patchwork.ozlabs.org/api/1.0/series/492243/?format=json","date":"2026-02-16T03:44:19","name":"target/arm: Support SME for KVM","version":1,"mbox":"http://patchwork.ozlabs.org/series/492243/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2196692/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=xq19cRc2;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fDpbb6NsVz1xpl\n\tfor ; Mon, 16 Feb 2026 14:46:19 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1vrpYE-00034K-VR; Sun, 15 Feb 2026 22:45:36 -0500","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1vrpXp-0002jp-Mh\n for qemu-devel@nongnu.org; Sun, 15 Feb 2026 22:45:12 -0500","from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1vrpXn-0002dx-3E\n for qemu-devel@nongnu.org; Sun, 15 Feb 2026 22:45:08 -0500","by mail-pg1-x532.google.com with SMTP id\n 41be03b00d2f7-c648bc907ebso1662240a12.3\n for ; Sun, 15 Feb 2026 19:45:05 -0800 (PST)","from stoup.. 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helo=mail-pg1-x532.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Add the properties even if SME is not supported, akin to how\nwe unconditionally add the SVE properties.\n\nSigned-off-by: Richard Henderson \n---\n target/arm/cpu64.c | 18 +++++++++++++++---\n 1 file changed, 15 insertions(+), 3 deletions(-)","diff":"diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c\nindex 38d06af49f..4a7032ba72 100644\n--- a/target/arm/cpu64.c\n+++ b/target/arm/cpu64.c\n@@ -496,9 +496,20 @@ void aarch64_add_sme_properties(Object *obj)\n ARMCPU *cpu = ARM_CPU(obj);\n uint32_t vq;\n \n- object_property_add_bool(obj, \"sme\", cpu_arm_get_sme, cpu_arm_set_sme);\n- object_property_add_bool(obj, \"sme_fa64\", cpu_arm_get_sme_fa64,\n- cpu_arm_set_sme_fa64);\n+ if (cpu->sme_vq.supported) {\n+ object_property_add_bool(obj, \"sme\", cpu_arm_get_sme, cpu_arm_set_sme);\n+ } else {\n+ assert(!tcg_enabled());\n+ prop_add_stub_bool(obj, \"sme\");\n+ }\n+ /*\n+ * Only TCG allows FA64 to be configured; host virtualization\n+ * enables it if and only if the host cpu supports it.\n+ */\n+ if (tcg_enabled()) {\n+ object_property_add_bool(obj, \"sme_fa64\", cpu_arm_get_sme_fa64,\n+ cpu_arm_set_sme_fa64);\n+ }\n \n for (vq = 1; vq <= ARM_MAX_VQ; vq <<= 1) {\n char name[8];\n@@ -784,6 +795,7 @@ static void aarch64_host_initfn(Object *obj)\n #if defined(CONFIG_KVM)\n kvm_arm_set_cpu_features_from_host(cpu);\n aarch64_add_sve_properties(obj);\n+ aarch64_add_sme_properties(obj);\n #elif defined(CONFIG_HVF)\n hvf_arm_set_cpu_features_from_host(cpu);\n #elif defined(CONFIG_WHPX)\n","prefixes":["RFC","13/13"]}