{"id":2196686,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2196686/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260216034432.23912-5-richard.henderson@linaro.org>","date":"2026-02-16T03:44:23","name":"[RFC,04/13] target/arm: Init sve_vq in kvm_arm_set_cpu_features_from_host","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"74223d95eaa2807cb9f4ffba51da6017c249fc85","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.0/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260216034432.23912-5-richard.henderson@linaro.org/mbox/","series":[{"id":492243,"url":"http://patchwork.ozlabs.org/api/1.0/series/492243/?format=json","date":"2026-02-16T03:44:19","name":"target/arm: Support SME for KVM","version":1,"mbox":"http://patchwork.ozlabs.org/series/492243/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2196686/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Rjh+Dpr8;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fDpZy39zPz1xpl\n\tfor ; Mon, 16 Feb 2026 14:45:46 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1vrpXX-0002Ws-R9; Sun, 15 Feb 2026 22:44:51 -0500","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1vrpXV-0002WS-QD\n for qemu-devel@nongnu.org; Sun, 15 Feb 2026 22:44:49 -0500","from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1vrpXU-0002QG-63\n for qemu-devel@nongnu.org; Sun, 15 Feb 2026 22:44:49 -0500","by mail-pg1-x530.google.com with SMTP id\n 41be03b00d2f7-c6e2355739dso975953a12.2\n for ; Sun, 15 Feb 2026 19:44:47 -0800 (PST)","from stoup.. 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Remove a separate\ninitialization path in arm_cpu_sve_finalize.\nUnexport kvm_arm_sve_get_vls.\n\nSigned-off-by: Richard Henderson \n---\n target/arm/kvm_arm.h | 10 ------\n target/arm/cpu64.c | 20 +-----------\n target/arm/kvm-stub.c | 5 ---\n target/arm/kvm.c | 73 ++++++++++++++++---------------------------\n 4 files changed, 28 insertions(+), 80 deletions(-)","diff":"diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h\nindex cc0b374254..97549766ea 100644\n--- a/target/arm/kvm_arm.h\n+++ b/target/arm/kvm_arm.h\n@@ -124,16 +124,6 @@ bool kvm_arm_create_scratch_host_vcpu(int *fdarray,\n */\n void kvm_arm_destroy_scratch_host_vcpu(int *fdarray);\n \n-/**\n- * kvm_arm_sve_get_vls:\n- * @cpu: ARMCPU\n- *\n- * Get all the SVE vector lengths supported by the KVM host, setting\n- * the bits corresponding to their length in quadwords minus one\n- * (vq - 1) up to ARM_MAX_VQ. Return the resulting map.\n- */\n-uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu);\n-\n /**\n * kvm_arm_set_cpu_features_from_host:\n * @cpu: ARMCPU to set the features for\ndiff --git a/target/arm/cpu64.c b/target/arm/cpu64.c\nindex 10c6796548..0116b6cc88 100644\n--- a/target/arm/cpu64.c\n+++ b/target/arm/cpu64.c\n@@ -79,28 +79,10 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)\n */\n uint32_t vq_map = cpu->sve_vq.map;\n uint32_t vq_init = cpu->sve_vq.init;\n- uint32_t vq_supported;\n+ uint32_t vq_supported = cpu->sve_vq.supported;\n uint32_t vq_mask = 0;\n uint32_t tmp, vq, max_vq = 0;\n \n- /*\n- * CPU models specify a set of supported vector lengths which are\n- * enabled by default. Attempting to enable any vector length not set\n- * in the supported bitmap results in an error. When KVM is enabled we\n- * fetch the supported bitmap from the host.\n- */\n- if (kvm_enabled()) {\n- if (kvm_arm_sve_supported()) {\n- cpu->sve_vq.supported = kvm_arm_sve_get_vls(cpu);\n- vq_supported = cpu->sve_vq.supported;\n- } else {\n- assert(!cpu_isar_feature(aa64_sve, cpu));\n- vq_supported = 0;\n- }\n- } else {\n- vq_supported = cpu->sve_vq.supported;\n- }\n-\n /*\n * Process explicit sve properties.\n * From the properties, sve_vq_map implies sve_vq_init.\ndiff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c\nindex ea67deea52..f2de36aef3 100644\n--- a/target/arm/kvm-stub.c\n+++ b/target/arm/kvm-stub.c\n@@ -95,11 +95,6 @@ void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp)\n g_assert_not_reached();\n }\n \n-uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu)\n-{\n- g_assert_not_reached();\n-}\n-\n void kvm_arm_enable_mte(Object *cpuobj, Error **errp)\n {\n g_assert_not_reached();\ndiff --git a/target/arm/kvm.c b/target/arm/kvm.c\nindex e0fd79b78c..464356989b 100644\n--- a/target/arm/kvm.c\n+++ b/target/arm/kvm.c\n@@ -60,6 +60,7 @@ typedef struct ARMHostCPUFeatures {\n ARMISARegisters isar;\n uint64_t features;\n uint32_t target;\n+ uint32_t sve_vq_supported;\n const char *dtb_compatible;\n } ARMHostCPUFeatures;\n \n@@ -243,58 +244,34 @@ static int get_host_cpu_reg(int fd, ARMHostCPUFeatures *ahcf,\n return ret;\n }\n \n-uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu)\n+static uint32_t kvm_arm_sve_get_vls(int fd)\n {\n /* Only call this function if kvm_arm_sve_supported() returns true. */\n- static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS];\n- static bool probed;\n+ uint64_t vls[KVM_ARM64_SVE_VLS_WORDS];\n+ struct kvm_one_reg reg = {\n+ .id = KVM_REG_ARM64_SVE_VLS,\n+ .addr = (uint64_t)&vls[0],\n+ };\n uint32_t vq = 0;\n- int i;\n+ int ret;\n \n- /*\n- * KVM ensures all host CPUs support the same set of vector lengths.\n- * So we only need to create the scratch VCPUs once and then cache\n- * the results.\n- */\n- if (!probed) {\n- struct kvm_vcpu_init init = {\n- .target = -1,\n- .features[0] = (1 << KVM_ARM_VCPU_SVE),\n- };\n- struct kvm_one_reg reg = {\n- .id = KVM_REG_ARM64_SVE_VLS,\n- .addr = (uint64_t)&vls[0],\n- };\n- int fdarray[3], ret;\n-\n- probed = true;\n-\n- if (!kvm_arm_create_scratch_host_vcpu(fdarray, &init)) {\n- error_report(\"failed to create scratch VCPU with SVE enabled\");\n- abort();\n- }\n- ret = ioctl(fdarray[2], KVM_GET_ONE_REG, ®);\n- kvm_arm_destroy_scratch_host_vcpu(fdarray);\n- if (ret) {\n- error_report(\"failed to get KVM_REG_ARM64_SVE_VLS: %s\",\n- strerror(errno));\n- abort();\n- }\n-\n- for (i = KVM_ARM64_SVE_VLS_WORDS - 1; i >= 0; --i) {\n- if (vls[i]) {\n- vq = 64 - clz64(vls[i]) + i * 64;\n- break;\n- }\n- }\n- if (vq > ARM_MAX_VQ) {\n- warn_report(\"KVM supports vector lengths larger than \"\n- \"QEMU can enable\");\n- vls[0] &= MAKE_64BIT_MASK(0, ARM_MAX_VQ);\n- }\n+ ret = ioctl(fd, KVM_GET_ONE_REG, ®);\n+ if (ret) {\n+ error_report(\"failed to get KVM_REG_ARM64_SVE_VLS: %s\",\n+ strerror(errno));\n+ abort();\n }\n \n- return vls[0];\n+ for (int i = KVM_ARM64_SVE_VLS_WORDS - 1; i >= 0; --i) {\n+ if (vls[i]) {\n+ vq = 64 - clz64(vls[i]) + i * 64;\n+ break;\n+ }\n+ }\n+ if (vq > ARM_MAX_VQ) {\n+ warn_report(\"KVM supports vector lengths larger than QEMU can enable\");\n+ }\n+ return vls[0] & MAKE_64BIT_MASK(0, ARM_MAX_VQ);\n }\n \n static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)\n@@ -469,6 +446,9 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)\n * So only read the register if we set KVM_ARM_VCPU_SVE above.\n */\n err |= get_host_cpu_reg(fd, ahcf, ID_AA64ZFR0_EL1_IDX);\n+\n+ /* Read the set of supported vector lengths. */\n+ arm_host_cpu_features.sve_vq_supported = kvm_arm_sve_get_vls(fd);\n }\n }\n \n@@ -516,6 +496,7 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)\n cpu->kvm_target = arm_host_cpu_features.target;\n cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible;\n cpu->isar = arm_host_cpu_features.isar;\n+ cpu->sve_vq.supported = arm_host_cpu_features.sve_vq_supported;\n env->features = arm_host_cpu_features.features;\n }\n \n","prefixes":["RFC","04/13"]}