{"id":2196684,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2196684/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260216034432.23912-4-richard.henderson@linaro.org>","date":"2026-02-16T03:44:22","name":"[RFC,03/13] target/arm: Move kvm_arm_sve_get_vls within kvm.c","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f98ed2bac7c607ed33d96e09e9f5fbe4a8dfb2fb","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.0/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260216034432.23912-4-richard.henderson@linaro.org/mbox/","series":[{"id":492243,"url":"http://patchwork.ozlabs.org/api/1.0/series/492243/?format=json","date":"2026-02-16T03:44:19","name":"target/arm: Support SME for KVM","version":1,"mbox":"http://patchwork.ozlabs.org/series/492243/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2196684/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=rgPFn0YQ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fDpZd5n5Xz1xpl\n\tfor ; Mon, 16 Feb 2026 14:45:29 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1vrpXW-0002WT-10; Sun, 15 Feb 2026 22:44:50 -0500","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1vrpXT-0002WB-QJ\n for qemu-devel@nongnu.org; Sun, 15 Feb 2026 22:44:47 -0500","from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1vrpXS-0002Q1-3I\n for qemu-devel@nongnu.org; Sun, 15 Feb 2026 22:44:47 -0500","by mail-pl1-x635.google.com with SMTP id\n d9443c01a7336-2aaf43014d0so19548055ad.2\n for ; Sun, 15 Feb 2026 19:44:45 -0800 (PST)","from stoup.. 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helo=mail-pl1-x635.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Prepare to adjust the invocation point and visibility.\n\nSigned-off-by: Richard Henderson \n---\n target/arm/kvm.c | 108 +++++++++++++++++++++++------------------------\n 1 file changed, 54 insertions(+), 54 deletions(-)","diff":"diff --git a/target/arm/kvm.c b/target/arm/kvm.c\nindex ded582e0da..e0fd79b78c 100644\n--- a/target/arm/kvm.c\n+++ b/target/arm/kvm.c\n@@ -243,6 +243,60 @@ static int get_host_cpu_reg(int fd, ARMHostCPUFeatures *ahcf,\n return ret;\n }\n \n+uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu)\n+{\n+ /* Only call this function if kvm_arm_sve_supported() returns true. */\n+ static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS];\n+ static bool probed;\n+ uint32_t vq = 0;\n+ int i;\n+\n+ /*\n+ * KVM ensures all host CPUs support the same set of vector lengths.\n+ * So we only need to create the scratch VCPUs once and then cache\n+ * the results.\n+ */\n+ if (!probed) {\n+ struct kvm_vcpu_init init = {\n+ .target = -1,\n+ .features[0] = (1 << KVM_ARM_VCPU_SVE),\n+ };\n+ struct kvm_one_reg reg = {\n+ .id = KVM_REG_ARM64_SVE_VLS,\n+ .addr = (uint64_t)&vls[0],\n+ };\n+ int fdarray[3], ret;\n+\n+ probed = true;\n+\n+ if (!kvm_arm_create_scratch_host_vcpu(fdarray, &init)) {\n+ error_report(\"failed to create scratch VCPU with SVE enabled\");\n+ abort();\n+ }\n+ ret = ioctl(fdarray[2], KVM_GET_ONE_REG, ®);\n+ kvm_arm_destroy_scratch_host_vcpu(fdarray);\n+ if (ret) {\n+ error_report(\"failed to get KVM_REG_ARM64_SVE_VLS: %s\",\n+ strerror(errno));\n+ abort();\n+ }\n+\n+ for (i = KVM_ARM64_SVE_VLS_WORDS - 1; i >= 0; --i) {\n+ if (vls[i]) {\n+ vq = 64 - clz64(vls[i]) + i * 64;\n+ break;\n+ }\n+ }\n+ if (vq > ARM_MAX_VQ) {\n+ warn_report(\"KVM supports vector lengths larger than \"\n+ \"QEMU can enable\");\n+ vls[0] &= MAKE_64BIT_MASK(0, ARM_MAX_VQ);\n+ }\n+ }\n+\n+ return vls[0];\n+}\n+\n static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)\n {\n /* Identify the feature bits corresponding to the host CPU, and\n@@ -1886,60 +1940,6 @@ bool kvm_arm_mte_supported(void)\n \n QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1);\n \n-uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu)\n-{\n- /* Only call this function if kvm_arm_sve_supported() returns true. */\n- static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS];\n- static bool probed;\n- uint32_t vq = 0;\n- int i;\n-\n- /*\n- * KVM ensures all host CPUs support the same set of vector lengths.\n- * So we only need to create the scratch VCPUs once and then cache\n- * the results.\n- */\n- if (!probed) {\n- struct kvm_vcpu_init init = {\n- .target = -1,\n- .features[0] = (1 << KVM_ARM_VCPU_SVE),\n- };\n- struct kvm_one_reg reg = {\n- .id = KVM_REG_ARM64_SVE_VLS,\n- .addr = (uint64_t)&vls[0],\n- };\n- int fdarray[3], ret;\n-\n- probed = true;\n-\n- if (!kvm_arm_create_scratch_host_vcpu(fdarray, &init)) {\n- error_report(\"failed to create scratch VCPU with SVE enabled\");\n- abort();\n- }\n- ret = ioctl(fdarray[2], KVM_GET_ONE_REG, ®);\n- kvm_arm_destroy_scratch_host_vcpu(fdarray);\n- if (ret) {\n- error_report(\"failed to get KVM_REG_ARM64_SVE_VLS: %s\",\n- strerror(errno));\n- abort();\n- }\n-\n- for (i = KVM_ARM64_SVE_VLS_WORDS - 1; i >= 0; --i) {\n- if (vls[i]) {\n- vq = 64 - clz64(vls[i]) + i * 64;\n- break;\n- }\n- }\n- if (vq > ARM_MAX_VQ) {\n- warn_report(\"KVM supports vector lengths larger than \"\n- \"QEMU can enable\");\n- vls[0] &= MAKE_64BIT_MASK(0, ARM_MAX_VQ);\n- }\n- }\n-\n- return vls[0];\n-}\n-\n static int kvm_arm_sve_set_vls(ARMCPU *cpu)\n {\n uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq.map };\n","prefixes":["RFC","03/13"]}