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51494b6f-ff5d-4f33-9f53-08de6d02eb92","X-MS-Exchange-CrossTenant-AuthSource":"\n SI2PR01MB4393.apcprd01.prod.exchangelabs.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"16 Feb 2026 02:27:24.6939\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa","X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg":"\n\t00000000-0000-0000-0000-000000000000","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"SEYPR01MB5340"},"content":"The ACS Enhanced Capability introduces several new access controls to\nimprove device isolation. These new controls are particularly important\nfor device passthrough in virtualization scenarios.\n\nFor example, a DMA transaction from a device may target a guest physical\naddress that lies within the memory aperture of the switch's upstream\nport, but not within any memory aperture or BAR space of a downstream\nport. In such cases, the switch would generate an Unsupported Request (UR)\nresponse to the device, which is undesirable. Enabling Unclaimed Request\nRedirect Control ensures that these DMA requests are forwarded upstream\ninstead of being rejected.\n\nThe ACS DSP and USP Memory Target Access Control and ACS I/O Request\nBlocking features similarly enhance device isolation. Device grouping in\nLinux assumes that devices are properly isolated. Therefore, enable these\ncontrols by default if PCI_ACS_ECAP is supported by the hardware. As with\nother basic ACS access controls, these new controls can be configured via\nthe \"config_acs=\" boot parameter.\n\nSigned-off-by: Wei Wang \nReviewed-by: Jason Gunthorpe \n---\n .../admin-guide/kernel-parameters.txt | 23 +++++++++++++------\n drivers/pci/pci.c | 10 ++++++++\n include/uapi/linux/pci_regs.h | 13 +++++++++++\n 3 files changed, 39 insertions(+), 7 deletions(-)","diff":"diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt\nindex bfd13197658f..f8444fea9914 100644\n--- a/Documentation/admin-guide/kernel-parameters.txt\n+++ b/Documentation/admin-guide/kernel-parameters.txt\n@@ -5281,13 +5281,22 @@ Kernel parameters\n \t\t\t\tflags.\n \n \t\t\t\tACS Flags is defined as follows:\n-\t\t\t\t bit-0 : ACS Source Validation\n-\t\t\t\t bit-1 : ACS Translation Blocking\n-\t\t\t\t bit-2 : ACS P2P Request Redirect\n-\t\t\t\t bit-3 : ACS P2P Completion Redirect\n-\t\t\t\t bit-4 : ACS Upstream Forwarding\n-\t\t\t\t bit-5 : ACS P2P Egress Control\n-\t\t\t\t bit-6 : ACS Direct Translated P2P\n+\t\t\t\t bit-0 : ACS Source Validation\n+\t\t\t\t bit-1 : ACS Translation Blocking\n+\t\t\t\t bit-2 : ACS P2P Request Redirect\n+\t\t\t\t bit-3 : ACS P2P Completion Redirect\n+\t\t\t\t bit-4 : ACS Upstream Forwarding\n+\t\t\t\t bit-5 : ACS P2P Egress Control\n+\t\t\t\t bit-6 : ACS Direct Translated P2P\n+\t\t\t\t bit-7 : ACS I/O Request Blocking\n+\t\t\t\t bit-9:8 : ACS DSP Memory Target Access Ctrl\n+\t\t\t\t 00 : Direct Request access enabled\n+\t\t\t\t 01 : Request blocking enabled\n+\t\t\t\t 10 : Request redirect enabled\n+\t\t\t\t 11 : Reserved\n+\t\t\t\t bit-11:10 : ACS USP Memory Target Access Ctrl\n+\t\t\t\t Same encoding as bit-9:8\n+\t\t\t\t bit-12 : ACS Unclaimed Request Redirect Ctrl\n \t\t\t\tEach bit can be marked as:\n \t\t\t\t '0' – force disabled\n \t\t\t\t '1' – force enabled\ndiff --git a/drivers/pci/pci.c b/drivers/pci/pci.c\nindex 4b32fbbcacb6..c34780a5f886 100644\n--- a/drivers/pci/pci.c\n+++ b/drivers/pci/pci.c\n@@ -1039,6 +1039,16 @@ static void pci_std_enable_acs(struct pci_dev *dev, struct pci_acs *caps)\n \t/* Upstream Forwarding */\n \tcaps->ctrl |= (dev->acs_capabilities & PCI_ACS_UF);\n \n+\t/*\n+\t * Redirect Unclaimed Request Redirect Control, I/O Request Blocking,\n+\t * and Downstream and Upstream Port Memory Target Access Redirect.\n+\t */\n+\tif (dev->acs_capabilities & PCI_ACS_ECAP) {\n+\t\tcaps->ctrl |= PCI_ACS_URRC | PCI_ACS_IB;\n+\t\tFIELD_MODIFY(PCI_ACS_DMAC_MASK, &caps->ctrl, PCI_ACS_MAC_RR);\n+\t\tFIELD_MODIFY(PCI_ACS_UMAC_MASK, &caps->ctrl, PCI_ACS_MAC_RR);\n+\t}\n+\n \t/* Enable Translation Blocking for external devices and noats */\n \tif (pci_ats_disabled() || dev->external_facing || dev->untrusted)\n \t\tcaps->ctrl |= (dev->acs_capabilities & PCI_ACS_TB);\ndiff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h\nindex ec1c54b5a310..dcff29eb839b 100644\n--- a/include/uapi/linux/pci_regs.h\n+++ b/include/uapi/linux/pci_regs.h\n@@ -1016,6 +1016,7 @@\n \n /* Access Control Service */\n #define PCI_ACS_CAP\t\t0x04\t/* ACS Capability Register */\n+#define PCI_ACS_ECAP\t\t0x0080 /* ACS Enhanced Capability */\n #define PCI_ACS_SV\t\t0x0001\t/* Source Validation */\n #define PCI_ACS_TB\t\t0x0002\t/* Translation Blocking */\n #define PCI_ACS_RR\t\t0x0004\t/* P2P Request Redirect */\n@@ -1023,10 +1024,22 @@\n #define PCI_ACS_UF\t\t0x0010\t/* Upstream Forwarding */\n #define PCI_ACS_EC\t\t0x0020\t/* P2P Egress Control */\n #define PCI_ACS_DT\t\t0x0040\t/* Direct Translated P2P */\n+#define PCI_ACS_IB\t\t0x0080\t/* I/O Request Blocking */\n+#define PCI_ACS_DMAC_MASK\t0x0300 /* DSP Memory Target Access Control */\n+#define PCI_ACS_UMAC_MASK\t0x0C00 /* USP Memory Target Access Control */\n+#define PCI_ACS_URRC\t\t0x1000\t/* Unclaimed Request Redirect Ctrl */\n #define PCI_ACS_EGRESS_BITS\t0x05\t/* ACS Egress Control Vector Size */\n #define PCI_ACS_CTRL\t\t0x06\t/* ACS Control Register */\n #define PCI_ACS_EGRESS_CTL_V\t0x08\t/* ACS Egress Control Vector */\n \n+/* Encodings for DSP and USP Memory Target Access Control */\n+enum {\n+\tPCI_ACS_MAC_DA = 0x0,\t\t/* Direct request access */\n+\tPCI_ACS_MAC_RB = 0x1,\t\t/* Request blocking */\n+\tPCI_ACS_MAC_RR = 0x2,\t\t/* Request redirect */\n+\tPCI_ACS_MAC_RSVD = 0x3,\t\t/* Reserved */\n+};\n+\n /* SATA capability */\n #define PCI_SATA_REGS\t\t4\t/* SATA REGs specifier */\n #define PCI_SATA_REGS_MASK\t0xF\t/* location - BAR#/inline */\n","prefixes":["v5","5/6"]}