{"id":2196635,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2196635/?format=json","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.0/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260215163847.3522572-5-den@valinux.co.jp>","date":"2026-02-15T16:38:42","name":"[v7,4/9] PCI: dwc: Record integrated eDMA register window","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"981bb241d0180d4809748f98c919e4076d16bb26","submitter":{"id":91573,"url":"http://patchwork.ozlabs.org/api/1.0/people/91573/?format=json","name":"Koichiro Den","email":"den@valinux.co.jp"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260215163847.3522572-5-den@valinux.co.jp/mbox/","series":[{"id":492228,"url":"http://patchwork.ozlabs.org/api/1.0/series/492228/?format=json","date":"2026-02-15T16:38:38","name":"PCI: endpoint: pci-ep-msi: Add embedded doorbell fallback","version":7,"mbox":"http://patchwork.ozlabs.org/series/492228/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2196635/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=valinux.co.jp header.i=@valinux.co.jp\n header.a=rsa-sha256 header.s=selector1 header.b=WUsiEFdV;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n 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bh=IpMBWHmKo9m4Bn5DsWqxUnKAG8hRFfAVV32vx7GzjJU=;\n b=WUsiEFdVNlzjYtD2Joqtn6M+2mQ7sJHU5SoQta/bAeEe4njf665eU0Uf2WNj3KNIW941Wsa6RH7Y7OcuAeKS+tii2I1Df/Q7dWHt1nyXUAuSZjNsD9TAyn7q8vA1sNOrMWQOc/mBQzR2lmpZLZ1DPVkRZZ20dufIHZdS6NvKzUA=","From":"Koichiro Den ","To":"jingoohan1@gmail.com,\n\tmani@kernel.org,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\trobh@kernel.org,\n\tbhelgaas@google.com,\n\theiko@sntech.de,\n\tkishon@kernel.org,\n\tjdmason@kudzu.us,\n\tdave.jiang@intel.com,\n\tallenbh@gmail.com,\n\tcassel@kernel.org,\n\tshawn.lin@rock-chips.com,\n\tFrank.Li@nxp.com","Cc":"linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-rockchip@lists.infradead.org,\n\tntb@lists.linux.dev","Subject":"[PATCH v7 4/9] PCI: dwc: Record integrated eDMA register window","Date":"Mon, 16 Feb 2026 01:38:42 +0900","Message-ID":"<20260215163847.3522572-5-den@valinux.co.jp>","X-Mailer":"git-send-email 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rcP7IzkN6CBclMVwMxL0WjovxTQp9TRaXn2sPr+VJeCIu3QUPXx7Oefvxt3+mL2khNuJfef4hP9M4PTods1+o4PNasHKRmOmJO79gulG3RiUnhKdVwEv7HmHBUxqQs7PMYTnBuDhI2rP7NCQLnK+aFXCbjWsBbxX9/RewSTV3uVwhP/NN0b52X5kQgB0dIsth8SoA/QY+97GVIQNl+9IA1VVHdPQ+lHQq/DFpZxhlc4sYf67QJ0y7PShX8ECaboq0JnwqRV5mtG9To6r2HAkXjpU2sAPkbBupE2QoePtJL8F4TJtTKck6h31anXWvjPVp8zo5O5Xc5MmV0tDA4SlaOOS0eT1M4qdU03InCXc9S11KoWsp+D3FJVbCUz+W8rpqGGKL98cCJaDKf169lcU2G4aZCFR/kvIudOmldgSuI1zL6vpa6/bei5MPNHAUVhqeEU1SYrMjX+fFmMwyRKXKv9nDmFnBuRPxTXJObt8R2hh6hHaOEsJs1mb3RV2xbEofkMUYatMg/ETcK6vURNj2PJOSa1kIusPPpdU+1FIUfQhgoR5f48lAxpSXp1iCvnpS/KUoaklNO8plQIRtj0t1JKDaI1WFtUAhDel1AmAMSKdceIoym8Y1niHZARDCu7SY+t7byau0qUiPTrdL5UDrkm5VambGz6vIzCS3nJFKneHIjl+KK1+soP6+Ti5vR/UPzuLs70bxC7VEgKh1K8fD/aPhuJ6VlLRpEQ9hdsbCY/lltC1EwQnyz2mdoRlqHxF6qS9QusglndF0NMZJW+cY+mCWHPdUmzvN7EKEv3xIKdrfxd2IeeS0Yqe97AXwu23U3RBjIEeKwoOFg6FqdAt+27sjQjKyYDi3CpJ3fD9lQ+ozpiKge6BLUMFNIAfLuK8GeVMFOvP8UfR/EoEbYOfa75eLjLruWApkOXvDkICzs6shLBxM/h34jgmX9isjevFy5CiOKXvhHVGOzhmokqBATYohbtTd7AQ+8UzXXkRaqoiLEebt6XHN+eeQSMkJwyrgY2/q+z3vHOh9QOLaxznFjoiSZ9j/03xOYIQvwYbQr4tEAZFt3pArkfhp++43flIscRjBIKGPIKeG++IlK1VzP6Ti5nUPfq14ChlN4DughK8cgPy98O3bhm2Fn0MyZR6vYJ0Uocne5baQ/Wyn2vc+W9oNum+c6kEK6HxB1w878QB54/O0mLWxidwI6PQC6VxJClDwuXjNj2nefBGlTqAMGkQsupL7AGzezUiVwsgwDlRDtbgQ0oZ83RmYtaJ5NCzu9q6BGQUj905LUGbAWPRaC5z9o3UfMUUCekfPANtPlHsEh0/EclLJI7EGXKeyBCgklPkL08ia00y/E0S/LGxyckta4eczoCZ3+8ziz+/YpKXjQ7CkADxh+C37T0ekXSEM1lRFOUpH8t1URUVN/HwtjwUwJ5t1O+cBAqacqtDOHq3fCb7L+cWeCUu/2+gYk0g9Nu3S178NtSou8i1DmkenZ+prpPaqfr/HOcCqFG8tMcaNwCz3yf3ySvx9Aa/lUcQ88L1IphGbdQjE2NjdSqca1X0yp98+y0/TdyI1B/Dv8zVPcxS00ItGYHoBcBA8kjaZzOMo/EAUkxHApvlQH7JCSTmkkwCB4rBwQsKRlyuEYIMC9FpFH0lq1cR17KCNGK6DZ4BUwfy9kAlQfRHKGwmtzKKm6IhbAr2WuZ4YirdfFZX3QSsco5W2VrDiCkub8aHlpL9WRcLk2po3ssQDC2ceB0Tgbn0oh+mQsO0TleZXMvnjaKdncJ7+kcnM4FwiTYV","X-OriginatorOrg":"valinux.co.jp","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 4ab20b88-e354-40dc-e397-08de6cb0bb91","X-MS-Exchange-CrossTenant-AuthSource":"TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"15 Feb 2026 16:39:05.0491\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"7a57bee8-f73d-4c5f-a4f7-d72c91c8c111","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n YKEytzJbQbLhgu6W1DzOO4MxiaQAglo4pR5jFZ0iJfut1riEwZqxBmdZVWo9xU0O9jN6Lkda/1CqoBwHfK2Sow==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"OSCP286MB5196"},"content":"Some DesignWare PCIe controllers integrate an eDMA block whose registers\nare located in a dedicated register window. Endpoint function drivers\nmay need the physical base and size of this window to map/expose it to a\npeer.\n\nRecord the physical base and size of the integrated eDMA register window\nin struct dw_pcie.\n\nReviewed-by: Frank Li \nSigned-off-by: Koichiro Den \n---\n drivers/pci/controller/dwc/pcie-designware.c | 4 ++++\n drivers/pci/controller/dwc/pcie-designware.h | 2 ++\n 2 files changed, 6 insertions(+)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c\nindex 5741c09dde7f..f82ed189f6ae 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.c\n+++ b/drivers/pci/controller/dwc/pcie-designware.c\n@@ -162,8 +162,12 @@ int dw_pcie_get_resources(struct dw_pcie *pci)\n \t\t\tpci->edma.reg_base = devm_ioremap_resource(pci->dev, res);\n \t\t\tif (IS_ERR(pci->edma.reg_base))\n \t\t\t\treturn PTR_ERR(pci->edma.reg_base);\n+\t\t\tpci->edma_reg_phys = res->start;\n+\t\t\tpci->edma_reg_size = resource_size(res);\n \t\t} else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) {\n \t\t\tpci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET;\n+\t\t\tpci->edma_reg_phys = pci->atu_phys_addr + DEFAULT_DBI_DMA_OFFSET;\n+\t\t\tpci->edma_reg_size = pci->atu_size - DEFAULT_DBI_DMA_OFFSET;\n \t\t}\n \t}\n \ndiff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h\nindex ae6389dd9caa..52f26663e8b1 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.h\n+++ b/drivers/pci/controller/dwc/pcie-designware.h\n@@ -541,6 +541,8 @@ struct dw_pcie {\n \tint\t\t\tmax_link_speed;\n \tu8\t\t\tn_fts[2];\n \tstruct dw_edma_chip\tedma;\n+\tphys_addr_t\t\tedma_reg_phys;\n+\tresource_size_t\t\tedma_reg_size;\n \tbool\t\t\tl1ss_support;\t/* L1 PM Substates support */\n \tstruct clk_bulk_data\tapp_clks[DW_PCIE_NUM_APP_CLKS];\n \tstruct clk_bulk_data\tcore_clks[DW_PCIE_NUM_CORE_CLKS];\n","prefixes":["v7","4/9"]}