{"id":2196483,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2196483/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260214034135.220413-10-zhenzhong.duan@intel.com>","date":"2026-02-14T03:41:29","name":"[RFCv2,09/13] intel_iommu: Handle PASID entry removal for system reset","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"59fa90ff24003d22c033edcbdbc882df300348d4","submitter":{"id":81636,"url":"http://patchwork.ozlabs.org/api/1.0/people/81636/?format=json","name":"Duan, Zhenzhong","email":"zhenzhong.duan@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260214034135.220413-10-zhenzhong.duan@intel.com/mbox/","series":[{"id":492156,"url":"http://patchwork.ozlabs.org/api/1.0/series/492156/?format=json","date":"2026-02-14T03:41:20","name":"intel_iommu: Enable PASID support for passthrough device","version":1,"mbox":"http://patchwork.ozlabs.org/series/492156/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2196483/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=MLdTylPi;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=\"83666858\"","E=Sophos;i=\"6.21,289,1763452800\"; d=\"scan'208\";a=\"83666858\"","E=Sophos;i=\"6.21,289,1763452800\"; d=\"scan'208\";a=\"212933105\""],"X-ExtLoop1":"1","From":"Zhenzhong Duan ","To":"qemu-devel@nongnu.org","Cc":"alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan ","Subject":"[RFCv2 PATCH 09/13] intel_iommu: Handle PASID entry removal for\n system reset","Date":"Fri, 13 Feb 2026 22:41:29 -0500","Message-ID":"<20260214034135.220413-10-zhenzhong.duan@intel.com>","X-Mailer":"git-send-email 2.47.3","In-Reply-To":"<20260214034135.220413-1-zhenzhong.duan@intel.com>","References":"<20260214034135.220413-1-zhenzhong.duan@intel.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=198.175.65.12;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com","X-Spam_score_int":"-43","X-Spam_score":"-4.4","X-Spam_bar":"----","X-Spam_report":"(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"When system level reset, DMA translation is turned off, all PASID\nentries become stale and should be deleted.\n\nvtd_hiod list is never accessed without BQL, so no need to guard with\niommu lock.\n\nSigned-off-by: Zhenzhong Duan \n---\n hw/i386/intel_iommu_accel.h | 5 +++++\n hw/i386/intel_iommu.c | 2 ++\n hw/i386/intel_iommu_accel.c | 13 +++++++++++++\n 3 files changed, 20 insertions(+)","diff":"diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h\nindex a77fd06fe0..914c690c26 100644\n--- a/hw/i386/intel_iommu_accel.h\n+++ b/hw/i386/intel_iommu_accel.h\n@@ -28,6 +28,7 @@ void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s, uint16_t domain_id,\n uint32_t pasid, hwaddr addr,\n uint64_t npages, bool ih);\n void vtd_pasid_cache_sync_accel(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_info);\n+void vtd_pasid_cache_reset_accel(IntelIOMMUState *s);\n void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops);\n #else\n static inline bool vtd_check_hiod_accel(IntelIOMMUState *s,\n@@ -62,6 +63,10 @@ static inline void vtd_pasid_cache_sync_accel(IntelIOMMUState *s,\n {\n }\n \n+static inline void vtd_pasid_cache_reset_accel(IntelIOMMUState *s)\n+{\n+}\n+\n static inline void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops)\n {\n }\ndiff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\nindex bc7589a776..96c9a616a8 100644\n--- a/hw/i386/intel_iommu.c\n+++ b/hw/i386/intel_iommu.c\n@@ -391,6 +391,8 @@ static void vtd_reset_caches(IntelIOMMUState *s)\n vtd_reset_context_cache_locked(s);\n vtd_pasid_cache_reset_locked(s);\n vtd_iommu_unlock(s);\n+\n+ vtd_pasid_cache_reset_accel(s);\n }\n \n static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level)\ndiff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c\nindex 5a956af916..c1890ca0a5 100644\n--- a/hw/i386/intel_iommu_accel.c\n+++ b/hw/i386/intel_iommu_accel.c\n@@ -497,6 +497,19 @@ void vtd_pasid_cache_sync_accel(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_info)\n }\n }\n \n+/* Fake a gloal pasid cache invalidation to remove all pasid cache entries */\n+void vtd_pasid_cache_reset_accel(IntelIOMMUState *s)\n+{\n+ VTDPASIDCacheInfo pc_info = { .type = VTD_INV_DESC_PASIDC_G_GLOBAL };\n+ VTDHostIOMMUDevice *vtd_hiod;\n+ GHashTableIter as_it;\n+\n+ g_hash_table_iter_init(&as_it, s->vtd_host_iommu_dev);\n+ while (g_hash_table_iter_next(&as_it, NULL, (void **)&vtd_hiod)) {\n+ vtd_pasid_cache_invalidate(vtd_hiod, &pc_info);\n+ }\n+}\n+\n static uint64_t vtd_get_host_iommu_quirks(uint32_t type,\n void *caps, uint32_t size)\n {\n","prefixes":["RFCv2","09/13"]}