{"id":2196480,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2196480/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260214034135.220413-13-zhenzhong.duan@intel.com>","date":"2026-02-14T03:41:32","name":"[RFCv2,12/13] intel_iommu_accel: Add pasid bits size check","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a45daf379d31c3795c4a5fc99953e4204c4639ea","submitter":{"id":81636,"url":"http://patchwork.ozlabs.org/api/1.0/people/81636/?format=json","name":"Duan, Zhenzhong","email":"zhenzhong.duan@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260214034135.220413-13-zhenzhong.duan@intel.com/mbox/","series":[{"id":492156,"url":"http://patchwork.ozlabs.org/api/1.0/series/492156/?format=json","date":"2026-02-14T03:41:20","name":"intel_iommu: Enable PASID support for passthrough device","version":1,"mbox":"http://patchwork.ozlabs.org/series/492156/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2196480/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=VFSoW0ZL;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fCZdB6M7wz1xpY\n\tfor ; Sat, 14 Feb 2026 14:43:26 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1vr6YG-0005JD-1Z; Fri, 13 Feb 2026 22:42:36 -0500","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1vr6YF-0005Hz-71\n for qemu-devel@nongnu.org; Fri, 13 Feb 2026 22:42:35 -0500","from mgamail.intel.com ([198.175.65.12])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1vr6YD-0008J1-Kp\n for qemu-devel@nongnu.org; Fri, 13 Feb 2026 22:42:34 -0500","from orviesa009.jf.intel.com ([10.64.159.149])\n by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Feb 2026 19:42:33 -0800","from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Feb 2026 19:42:29 -0800"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1771040554; x=1802576554;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=SDpCFayu97R5owktLGHAkU9F+zX5Nl2NSUvxpfROTIE=;\n b=VFSoW0ZLsCVB4SFIzWwi2nY7v7ZQotzMXgHkakk4OSUGSNoUxZQcOW3A\n eYjQmkAc9GoSMcmq5YxLbKhVrUnhAdcdnPisYtH3h+UYAcWl6bdEiC9ZQ\n xRENjK+08mjZs31a8Z+LEgxoKHrmi23F1RrKqQcC1V0rH4U2faWRLNW13\n NuDMMkakuSclopH33L+lG7EqfqhbBIt6uhmu9KZITGXUVzXdKlZaiVnKO\n 4CxsB0KIBSIrClIO2zwSx9M3sMnI9WH+MNVRQCNB1BoEGX4/3gNDXfn8J\n zDJvteo8KYWiBxTHI+/Q+0IbTEvFeisYsI3W/6ANSfm1dy43afg2dKhz4 w==;","X-CSE-ConnectionGUID":["EqByieCcR2ixmcP/cFmWxg==","Q9A+0ZH+Q1mINV4PkNrjug=="],"X-CSE-MsgGUID":["vaT1F+OpQruyVgdqUyRpHg==","DyMFskqeSDW2xzh2ajFqKQ=="],"X-IronPort-AV":["E=McAfee;i=\"6800,10657,11700\"; a=\"83666877\"","E=Sophos;i=\"6.21,289,1763452800\"; d=\"scan'208\";a=\"83666877\"","E=Sophos;i=\"6.21,289,1763452800\"; d=\"scan'208\";a=\"212933129\""],"X-ExtLoop1":"1","From":"Zhenzhong Duan ","To":"qemu-devel@nongnu.org","Cc":"alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan ","Subject":"[RFCv2 PATCH 12/13] intel_iommu_accel: Add pasid bits size check","Date":"Fri, 13 Feb 2026 22:41:32 -0500","Message-ID":"<20260214034135.220413-13-zhenzhong.duan@intel.com>","X-Mailer":"git-send-email 2.47.3","In-Reply-To":"<20260214034135.220413-1-zhenzhong.duan@intel.com>","References":"<20260214034135.220413-1-zhenzhong.duan@intel.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=198.175.65.12;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com","X-Spam_score_int":"-43","X-Spam_score":"-4.4","X-Spam_bar":"----","X-Spam_report":"(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"If pasid bits size is bigger than host side, host could fail to emulate\nall bindings in guest. Add a check to fail device plug early.\n\nPasid bits size should also be no more than 20 bits according to PCI spec.\n\nSigned-off-by: Zhenzhong Duan \n---\n hw/i386/intel_iommu_internal.h | 1 +\n hw/i386/intel_iommu.c | 5 +++++\n hw/i386/intel_iommu_accel.c | 8 ++++++++\n 3 files changed, 14 insertions(+)","diff":"diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h\nindex e4bcc884b0..e5518a94ea 100644\n--- a/hw/i386/intel_iommu_internal.h\n+++ b/hw/i386/intel_iommu_internal.h\n@@ -195,6 +195,7 @@\n #define VTD_ECAP_MHMV (15ULL << 20)\n #define VTD_ECAP_SRS (1ULL << 31)\n #define VTD_ECAP_NWFS (1ULL << 33)\n+#define VTD_ECAP_PSS(x) extract64(x, 35, 5)\n #define VTD_ECAP_PASID (1ULL << 40)\n #define VTD_ECAP_PDS (1ULL << 42)\n #define VTD_ECAP_SMTS (1ULL << 43)\ndiff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\nindex 6483cb3d85..c1b31b17de 100644\n--- a/hw/i386/intel_iommu.c\n+++ b/hw/i386/intel_iommu.c\n@@ -5545,6 +5545,11 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)\n error_setg(errp, \"Need to set scalable mode for PASID\");\n return false;\n }\n+ if (s->pasid >= PCI_EXT_CAP_PASID_MAX_WIDTH) {\n+ error_setg(errp, \"PASID width %d, exceed Max PASID Width %d allowed \"\n+ \"in PCI spec\", s->pasid, PCI_EXT_CAP_PASID_MAX_WIDTH);\n+ return false;\n+ }\n \n if (s->svm) {\n if (!x86_iommu->dt_supported) {\ndiff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c\nindex acb1b1e238..15412123d5 100644\n--- a/hw/i386/intel_iommu_accel.c\n+++ b/hw/i386/intel_iommu_accel.c\n@@ -44,6 +44,7 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod,\n HostIOMMUDevice *hiod = vtd_hiod->hiod;\n struct HostIOMMUDeviceCaps *caps = &hiod->caps;\n struct iommu_hw_info_vtd *vtd = &caps->vendor_caps.vtd;\n+ uint8_t hpasid = VTD_ECAP_PSS(vtd->ecap_reg) + 1;\n PCIBus *bus = vtd_hiod->bus;\n PCIDevice *pdev = bus->devices[vtd_hiod->devfn];\n \n@@ -64,6 +65,13 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod,\n return false;\n }\n \n+ /* Only do the check when host device support PASIDs */\n+ if (caps->max_pasid_log2 && s->pasid > hpasid) {\n+ error_setg(errp, \"PASID bits size %d > host IOMMU PASID bits size %d\",\n+ s->pasid, hpasid);\n+ return false;\n+ }\n+\n if (pci_device_get_iommu_bus_devfn(pdev, &bus, NULL, NULL)) {\n error_setg(errp, \"Host device downstream to a PCI bridge is \"\n \"unsupported when x-flts=on\");\n","prefixes":["RFCv2","12/13"]}