{"id":2196475,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2196475/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260214034135.220413-14-zhenzhong.duan@intel.com>","date":"2026-02-14T03:41:33","name":"[RFCv2,13/13] intel_iommu: Expose flag VIOMMU_FLAG_PASID_SUPPORTED when configured","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"524e9c92d1c50e0a3a5e718f65994257170df937","submitter":{"id":81636,"url":"http://patchwork.ozlabs.org/api/1.0/people/81636/?format=json","name":"Duan, Zhenzhong","email":"zhenzhong.duan@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260214034135.220413-14-zhenzhong.duan@intel.com/mbox/","series":[{"id":492156,"url":"http://patchwork.ozlabs.org/api/1.0/series/492156/?format=json","date":"2026-02-14T03:41:20","name":"intel_iommu: Enable PASID support for passthrough device","version":1,"mbox":"http://patchwork.ozlabs.org/series/492156/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2196475/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=R4yUrio/;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Fri, 13 Feb 2026 22:42:38 -0500","from orviesa009.jf.intel.com ([10.64.159.149])\n by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Feb 2026 19:42:37 -0800","from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Feb 2026 19:42:33 -0800"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1771040557; x=1802576557;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=LiCckamDJARkM29it4+GmExQOwvpYcX1Aa4iyhrdEAY=;\n b=R4yUrio/slLBTnFmiUhQnzCzc08PpL4T0Qs9Gh3p0ZoKJnVj0KkkTLxa\n xr9GdI5J80l+i0hnvJQZHvmHszMOWdE3MsOaJ+foom++WYTJTG+yCB1pH\n b0cgmeGwtZ8Rmi+v79aYIGzAz6wl4Ikl1gd/cSxvGN89F5+f5szhKXLrS\n cgRxPvX4ScTPylhZe253tIO/7O1SR/TCr2IkrJhTO9XYErJETDhz6S95u\n TagBEhtlPZQksZpWDbXhIeDFOireDAO+a5dUpYmxBCdwGzr6EBLZpUQ4k\n zllj0ZSNfzMxylJ5kb4Mm7gZ2jCZAAilmVa/71/z8X9x+/RoGYkgO9g3g g==;","X-CSE-ConnectionGUID":["j6fvcX5FTUaEWPHCb7Uv6w==","1EdsHg3KSRGE75K46MBj4A=="],"X-CSE-MsgGUID":["XPbW8WknSoa0OzMsnffocw==","CaqArC9nTE62g4RC1zUZRA=="],"X-IronPort-AV":["E=McAfee;i=\"6800,10657,11700\"; a=\"83666883\"","E=Sophos;i=\"6.21,289,1763452800\"; d=\"scan'208\";a=\"83666883\"","E=Sophos;i=\"6.21,289,1763452800\"; d=\"scan'208\";a=\"212933147\""],"X-ExtLoop1":"1","From":"Zhenzhong Duan ","To":"qemu-devel@nongnu.org","Cc":"alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan ","Subject":"[RFCv2 PATCH 13/13] intel_iommu: Expose flag\n VIOMMU_FLAG_PASID_SUPPORTED when configured","Date":"Fri, 13 Feb 2026 22:41:33 -0500","Message-ID":"<20260214034135.220413-14-zhenzhong.duan@intel.com>","X-Mailer":"git-send-email 2.47.3","In-Reply-To":"<20260214034135.220413-1-zhenzhong.duan@intel.com>","References":"<20260214034135.220413-1-zhenzhong.duan@intel.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=198.175.65.12;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com","X-Spam_score_int":"-43","X-Spam_score":"-4.4","X-Spam_bar":"----","X-Spam_report":"(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"VFIO device will check flag VIOMMU_FLAG_PASID_SUPPORTED and expose PASID\ncapability, or else guest could not enable PASID of this device even if\nvIOMMU's pasid is configured.\n\nThis is the final knob to enable PASID.\n\nSigned-off-by: Zhenzhong Duan \n---\n hw/i386/intel_iommu.c | 1 +\n 1 file changed, 1 insertion(+)","diff":"diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\nindex c1b31b17de..eaf384f40b 100644\n--- a/hw/i386/intel_iommu.c\n+++ b/hw/i386/intel_iommu.c\n@@ -4779,6 +4779,7 @@ static uint64_t vtd_get_viommu_flags(void *opaque)\n uint64_t flags;\n \n flags = s->fsts ? VIOMMU_FLAG_WANT_NESTING_PARENT : 0;\n+ flags |= s->pasid ? VIOMMU_FLAG_PASID_SUPPORTED : 0;\n \n return flags;\n }\n","prefixes":["RFCv2","13/13"]}