{"id":2196474,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2196474/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260214034135.220413-7-zhenzhong.duan@intel.com>","date":"2026-02-14T03:41:26","name":"[RFCv2,06/13] intel_iommu: Export some functions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e85868af388a6e4b522f1dc692af7a379b866589","submitter":{"id":81636,"url":"http://patchwork.ozlabs.org/api/1.0/people/81636/?format=json","name":"Duan, Zhenzhong","email":"zhenzhong.duan@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260214034135.220413-7-zhenzhong.duan@intel.com/mbox/","series":[{"id":492156,"url":"http://patchwork.ozlabs.org/api/1.0/series/492156/?format=json","date":"2026-02-14T03:41:20","name":"intel_iommu: Enable PASID support for passthrough device","version":1,"mbox":"http://patchwork.ozlabs.org/series/492156/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2196474/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=kEUIu04A;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Fri, 13 Feb 2026 22:42:12 -0500","from orviesa009.jf.intel.com ([10.64.159.149])\n by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Feb 2026 19:42:10 -0800","from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Feb 2026 19:42:06 -0800"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1771040531; x=1802576531;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=VHorsJz4aqaEhjxNJ20oCh3okyulXgR95PzP5Z+GvaA=;\n b=kEUIu04AqH9w2kzpPe5h6lD84s5UcoukeHINzLqINFUsrjouCXlnSV67\n lYk1PDYAV4+qlJn/a+wpgiR4wiSyoWAwQ+3giCKPOaLivbzdt9iHQjGqR\n tWakBYh4+Wm4xS5nwea8/n/zKh5eTzti0pIKzxjDPjWla/KyhXa1GPUN+\n QMDQc0tq8asz+aenAJJ+1b4WNFyZWR+wuUb+lVSavEJ4d1oguSy/BfMtr\n Fmrv9061ia/qnB9B0bjW/NBTVU1eYIvUB8tNY1JErvvXbtaJ0mYkRPlmT\n 0/8cGTeAPTESVENZSwRkYOe5skPfdlXfG2i7fuhSoR2md/DXkbl9IGC9i A==;","X-CSE-ConnectionGUID":["FGZjIH8gRYGWR+clWF2ciQ==","VEfS5l9OSVSldpdxLvMZ+g=="],"X-CSE-MsgGUID":["Rs59cnNaQUu19DONosrgwQ==","EXtFf3zPTF27TdNbal9PQg=="],"X-IronPort-AV":["E=McAfee;i=\"6800,10657,11700\"; a=\"83666833\"","E=Sophos;i=\"6.21,289,1763452800\"; d=\"scan'208\";a=\"83666833\"","E=Sophos;i=\"6.21,289,1763452800\"; d=\"scan'208\";a=\"212933050\""],"X-ExtLoop1":"1","From":"Zhenzhong Duan ","To":"qemu-devel@nongnu.org","Cc":"alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan ","Subject":"[RFCv2 PATCH 06/13] intel_iommu: Export some functions","Date":"Fri, 13 Feb 2026 22:41:26 -0500","Message-ID":"<20260214034135.220413-7-zhenzhong.duan@intel.com>","X-Mailer":"git-send-email 2.47.3","In-Reply-To":"<20260214034135.220413-1-zhenzhong.duan@intel.com>","References":"<20260214034135.220413-1-zhenzhong.duan@intel.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=198.175.65.12;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com","X-Spam_score_int":"-43","X-Spam_score":"-4.4","X-Spam_bar":"----","X-Spam_report":"(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Export some functions for accel code usages. Inline functions and MACROs\nare moved to internal header files. Then accel code in following patches\ncould access them.\n\nSigned-off-by: Zhenzhong Duan \nReviewed-by: Clement Mathieu--Drif \n---\n hw/i386/intel_iommu_internal.h | 31 +++++++++++++++++++++++++\n hw/i386/intel_iommu.c | 42 ++++++++--------------------------\n 2 files changed, 40 insertions(+), 33 deletions(-)","diff":"diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h\nindex 04a9392e8a..8b020fb3a4 100644\n--- a/hw/i386/intel_iommu_internal.h\n+++ b/hw/i386/intel_iommu_internal.h\n@@ -619,6 +619,12 @@ typedef struct VTDRootEntry VTDRootEntry;\n #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL\n #define VTD_SM_CONTEXT_ENTRY_PRE 0x10ULL\n \n+/* context entry operations */\n+#define VTD_CE_GET_PASID_DIR_TABLE(ce) \\\n+ ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK)\n+#define VTD_CE_GET_PRE(ce) \\\n+ ((ce)->val[0] & VTD_SM_CONTEXT_ENTRY_PRE)\n+\n typedef struct VTDPASIDCacheInfo {\n uint8_t type;\n uint16_t did;\n@@ -745,4 +751,29 @@ static inline bool vtd_pe_pgtt_is_fst(VTDPASIDEntry *pe)\n {\n return (VTD_SM_PASID_ENTRY_PGTT(pe) == VTD_SM_PASID_ENTRY_FST);\n }\n+\n+static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire)\n+{\n+ return pdire->val & 1;\n+}\n+\n+static inline bool vtd_pe_present(VTDPASIDEntry *pe)\n+{\n+ return pe->val[0] & VTD_PASID_ENTRY_P;\n+}\n+\n+static inline int vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry *p2)\n+{\n+ return memcmp(p1, p2, sizeof(*p1));\n+}\n+\n+int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, uint32_t pasid,\n+ VTDPASIDDirEntry *pdire);\n+int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, uint32_t pasid,\n+ dma_addr_t addr, VTDPASIDEntry *pe);\n+int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,\n+ uint8_t devfn, VTDContextEntry *ce);\n+int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce,\n+ VTDPASIDEntry *pe, uint32_t pasid);\n+VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid);\n #endif\ndiff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\nindex e27a7c725f..d257dd95f6 100644\n--- a/hw/i386/intel_iommu.c\n+++ b/hw/i386/intel_iommu.c\n@@ -42,12 +42,6 @@\n #include \"migration/vmstate.h\"\n #include \"trace.h\"\n \n-/* context entry operations */\n-#define VTD_CE_GET_PASID_DIR_TABLE(ce) \\\n- ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK)\n-#define VTD_CE_GET_PRE(ce) \\\n- ((ce)->val[0] & VTD_SM_CONTEXT_ENTRY_PRE)\n-\n /*\n * Paging mode for first-stage translation (VTD spec Figure 9-6)\n * 00: 4-level paging, 01: 5-level paging\n@@ -831,18 +825,12 @@ static inline bool vtd_pe_type_check(IntelIOMMUState *s, VTDPASIDEntry *pe)\n }\n }\n \n-static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire)\n-{\n- return pdire->val & 1;\n-}\n-\n /**\n * Caller of this function should check present bit if wants\n * to use pdir entry for further usage except for fpd bit check.\n */\n-static int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base,\n- uint32_t pasid,\n- VTDPASIDDirEntry *pdire)\n+int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, uint32_t pasid,\n+ VTDPASIDDirEntry *pdire)\n {\n uint32_t index;\n dma_addr_t addr, entry_size;\n@@ -860,15 +848,8 @@ static int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base,\n return 0;\n }\n \n-static inline bool vtd_pe_present(VTDPASIDEntry *pe)\n-{\n- return pe->val[0] & VTD_PASID_ENTRY_P;\n-}\n-\n-static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s,\n- uint32_t pasid,\n- dma_addr_t addr,\n- VTDPASIDEntry *pe)\n+int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, uint32_t pasid,\n+ dma_addr_t addr, VTDPASIDEntry *pe)\n {\n uint8_t pgtt;\n uint32_t index;\n@@ -954,8 +935,8 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState *s,\n return 0;\n }\n \n-static int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce,\n- VTDPASIDEntry *pe, uint32_t pasid)\n+int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce,\n+ VTDPASIDEntry *pe, uint32_t pasid)\n {\n dma_addr_t pasid_dir_base;\n \n@@ -1531,8 +1512,8 @@ static int vtd_ce_pasid_0_check(IntelIOMMUState *s, VTDContextEntry *ce)\n }\n \n /* Map a device to its corresponding domain (context-entry) */\n-static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,\n- uint8_t devfn, VTDContextEntry *ce)\n+int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,\n+ uint8_t devfn, VTDContextEntry *ce)\n {\n VTDRootEntry re;\n int ret_fr;\n@@ -1894,7 +1875,7 @@ static VTDAddressSpace *vtd_get_as_by_sid_and_pasid(IntelIOMMUState *s,\n vtd_find_as_by_sid_and_pasid, &key);\n }\n \n-static VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid)\n+VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid)\n {\n return vtd_get_as_by_sid_and_pasid(s, sid, PCI_NO_PASID);\n }\n@@ -3116,11 +3097,6 @@ static inline int vtd_dev_get_pe_from_pasid(VTDAddressSpace *vtd_as,\n return vtd_ce_get_pasid_entry(s, &ce, pe, vtd_as->pasid);\n }\n \n-static int vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry *p2)\n-{\n- return memcmp(p1, p2, sizeof(*p1));\n-}\n-\n /* Update or invalidate pasid cache based on the pasid entry in guest memory. */\n static void vtd_pasid_cache_sync_locked(gpointer key, gpointer value,\n gpointer user_data)\n","prefixes":["RFCv2","06/13"]}