{"id":2196404,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2196404/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260213182713.44924-2-philmd@linaro.org>","date":"2026-02-13T18:27:09","name":"[1/5] qemu/target_info: Add target_page_bits_vary() helper","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"3b0787b42b2348d77f1c98bd2cca468622d61784","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/1.0/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260213182713.44924-2-philmd@linaro.org/mbox/","series":[{"id":492130,"url":"http://patchwork.ozlabs.org/api/1.0/series/492130/?format=json","date":"2026-02-13T18:27:09","name":"page-vary: Build set_preferred_target_page_bits() as common code","version":1,"mbox":"http://patchwork.ozlabs.org/series/492130/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2196404/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=S/xx7x+E;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::331;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Add a helper returning whether a target support variable\npage sizes (only ARM targets so far).\n\nSigned-off-by: Philippe Mathieu-Daudé \n---\n include/qemu/target-info-impl.h | 2 ++\n include/qemu/target-info.h | 7 +++++++\n configs/targets/aarch64-softmmu.c | 1 +\n configs/targets/arm-softmmu.c | 1 +\n target-info-stub.c | 5 +++++\n target-info.c | 5 +++++\n 6 files changed, 21 insertions(+)","diff":"diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h\nindex e446585bf53..537aad04fa8 100644\n--- a/include/qemu/target-info-impl.h\n+++ b/include/qemu/target-info-impl.h\n@@ -19,6 +19,8 @@ typedef struct TargetInfo {\n SysEmuTarget target_arch;\n /* runtime equivalent of TARGET_LONG_BITS definition */\n unsigned long_bits;\n+ /* runtime equivalent of TARGET_PAGE_BITS_VARY definition */\n+ bool page_bits_vary;\n /* runtime equivalent of CPU_RESOLVING_TYPE definition */\n const char *cpu_type;\n /* QOM typename machines for this binary must implement */\ndiff --git a/include/qemu/target-info.h b/include/qemu/target-info.h\nindex e3287334304..0d2269e0401 100644\n--- a/include/qemu/target-info.h\n+++ b/include/qemu/target-info.h\n@@ -23,6 +23,13 @@ const char *target_name(void);\n */\n unsigned target_long_bits(void);\n \n+/**\n+ * target_page_bits_vary:\n+ *\n+ * Returns: whether the target support variable page sizes\n+ */\n+bool target_page_bits_vary(void);\n+\n /**\n * target_machine_typename:\n *\ndiff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c\nindex 4e1e2f64da1..f9fb73a41c6 100644\n--- a/configs/targets/aarch64-softmmu.c\n+++ b/configs/targets/aarch64-softmmu.c\n@@ -15,6 +15,7 @@ static const TargetInfo target_info_aarch64_system = {\n .target_name = \"aarch64\",\n .target_arch = SYS_EMU_TARGET_AARCH64,\n .long_bits = 64,\n+ .page_bits_vary = true,\n .cpu_type = TYPE_ARM_CPU,\n .machine_typename = TYPE_TARGET_AARCH64_MACHINE,\n .endianness = ENDIAN_MODE_LITTLE,\ndiff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c\nindex 9b3fdd2854a..a3bca3c9f0d 100644\n--- a/configs/targets/arm-softmmu.c\n+++ b/configs/targets/arm-softmmu.c\n@@ -15,6 +15,7 @@ static const TargetInfo target_info_arm_system = {\n .target_name = \"arm\",\n .target_arch = SYS_EMU_TARGET_ARM,\n .long_bits = 32,\n+ .page_bits_vary = true,\n .cpu_type = TYPE_ARM_CPU,\n .machine_typename = TYPE_TARGET_ARM_MACHINE,\n .endianness = ENDIAN_MODE_LITTLE,\ndiff --git a/target-info-stub.c b/target-info-stub.c\nindex 65220cc7820..a6a080295f0 100644\n--- a/target-info-stub.c\n+++ b/target-info-stub.c\n@@ -20,6 +20,11 @@ static const TargetInfo target_info_stub = {\n .target_name = TARGET_NAME,\n .target_arch = glue(SYS_EMU_TARGET_, TARGET_ARCH),\n .long_bits = TARGET_LONG_BITS,\n+#ifdef TARGET_PAGE_BITS_VARY\n+ .page_bits_vary = true,\n+#else\n+ .page_bits_vary = false,\n+#endif\n .cpu_type = CPU_RESOLVING_TYPE,\n .machine_typename = TYPE_MACHINE,\n .endianness = TARGET_BIG_ENDIAN ? ENDIAN_MODE_BIG : ENDIAN_MODE_LITTLE,\ndiff --git a/target-info.c b/target-info.c\nindex a26532f660f..06bf329de72 100644\n--- a/target-info.c\n+++ b/target-info.c\n@@ -22,6 +22,11 @@ unsigned target_long_bits(void)\n return target_info()->long_bits;\n }\n \n+bool target_page_bits_vary(void)\n+{\n+ return target_info()->page_bits_vary;\n+}\n+\n SysEmuTarget target_arch(void)\n {\n return target_info()->target_arch;\n","prefixes":["1/5"]}