{"id":2196337,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2196337/?format=json","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.0/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260213084956.1031000-4-brian.ruley@gehealthcare.com>","date":"2026-02-13T08:49:52","name":"[v3,3/6] clk: imx6q: add ipu and ldb clocks and dependencies","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"563e835ad66e90009306634cc3a60ec42cdb54f5","submitter":{"id":89422,"url":"http://patchwork.ozlabs.org/api/1.0/people/89422/?format=json","name":"Brian Ruley","email":"brian.ruley@gehealthcare.com"},"delegate":{"id":151988,"url":"http://patchwork.ozlabs.org/api/1.0/users/151988/?format=json","username":"festevam","first_name":"Fabio","last_name":"Estevam","email":"festevam@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260213084956.1031000-4-brian.ruley@gehealthcare.com/mbox/","series":[{"id":492095,"url":"http://patchwork.ozlabs.org/api/1.0/series/492095/?format=json","date":"2026-02-13T08:49:49","name":"Enable the IPUv3 driver to use CCF","version":3,"mbox":"http://patchwork.ozlabs.org/series/492095/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2196337/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gehealthcare.com header.i=@gehealthcare.com\n header.a=rsa-sha256 header.s=selector1 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add ipu and ldb clocks and dependencies","Date":"Fri, 13 Feb 2026 10:49:52 +0200","Message-Id":"<20260213084956.1031000-4-brian.ruley@gehealthcare.com>","X-Mailer":"git-send-email 2.39.5","In-Reply-To":"<20260213084956.1031000-1-brian.ruley@gehealthcare.com>","References":"<\"aYtUi1WdLPLEnv2X@zoo11.em.health.ge.com\">\n <20260213084956.1031000-1-brian.ruley@gehealthcare.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"CH1PEPF0000A34C:EE_|PH3PPF44669FFFD:EE_","Content-Type":"text/plain","X-MS-Office365-Filtering-Correlation-Id":"57068064-f743-42be-2e92-08de6adce2c2","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"BCL:0;\n ARA:13230040|376014|82310400026|1800799024|36860700013;","X-Microsoft-Antispam-Message-Info":"\n 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57068064-f743-42be-2e92-08de6adce2c2","X-MS-Exchange-CrossTenant-Id":"9a309606-d6ec-4188-a28a-298812b4bbbf","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=9a309606-d6ec-4188-a28a-298812b4bbbf; Ip=[165.85.157.49];\n Helo=[mkerelay2.compute.ge-healthcare.net]","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"\n TreatMessagesAsInternal-CH1PEPF0000A34C.namprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"PH3PPF44669FFFD","X-Mailman-Approved-At":"Fri, 13 Feb 2026 14:24:08 +0100","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"This is required for the IPUv3 driver to migrate to CCF, changes are\nlargely based on the Linux kernel equivalent.\n\nAdd new gate2_flags function (also present in the Linux code) to set\nrequired flags.\n\nAdd usboh clock to get rid of error.\n\nSigned-off-by: Brian Ruley \n---\n\nChanges in v3:\n- Added HDMI clocks\n\n drivers/clk/imx/clk-imx6q.c | 334 +++++++++++++++++++++++++++++++++---\n drivers/clk/imx/clk.h | 9 +\n 2 files changed, 322 insertions(+), 21 deletions(-)","diff":"diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c\nindex f11f9045abb..f57ac79f8ca 100644\n--- a/drivers/clk/imx/clk-imx6q.c\n+++ b/drivers/clk/imx/clk-imx6q.c\n@@ -13,6 +13,21 @@\n \n #include \"clk.h\"\n \n+#define SET_CLK_RATE(id, rate) \\\n+\tdo { \\\n+\t\tstruct clk *clk; \\\n+\t\tclk_get_by_id(id, &clk); \\\n+\t\tclk_set_rate(clk, rate); \\\n+\t} while (0)\n+\n+#define SET_CLK_PARENT(child_id, parent_id) \\\n+\tdo { \\\n+\t\tstruct clk *clk, *clk_parent; \\\n+\t\tclk_get_by_id(parent_id, &clk_parent); \\\n+\t\tclk_get_by_id(child_id, &clk); \\\n+\t\tclk_set_parent(clk, clk_parent); \\\n+\t} while (0)\n+\n static int imx6q_clk_request(struct clk *clk)\n {\n \tif (clk->id < IMX6QDL_CLK_DUMMY || clk->id >= IMX6QDL_CLK_END) {\n@@ -39,6 +54,10 @@ static const char *const periph_sels[] = {\n \t\"periph_pre\",\n \t\"periph_clk2\",\n };\n+static const char *periph2_sels[] = {\n+\t\"periph2_pre\",\n+\t\"periph2_clk2\",\n+};\n static const char *const periph_pre_sels[] = {\n \t\"pll2_bus\",\n \t\"pll2_pfd2_396m\",\n@@ -53,6 +72,46 @@ static const char *const ecspi_sels[] = {\n \t\"pll3_60m\",\n \t\"osc\",\n };\n+static const char *const ipu_sels[] = {\n+\t\"mmdc_ch0_axi\",\n+\t\"pll2_pfd2_396m\",\n+\t\"pll3_120m\",\n+\t\"pll3_pfd1_540m\",\n+};\n+static const char *const ldb_di_sels[] = {\n+\t\"pll5_video_div\", \"pll2_pfd0_352m\", \"pll2_pfd2_396m\",\n+\t\"mmdc_ch1_axi\",\t \"pll3_usb_otg\",\n+};\n+static const char *const ipu_di_pre_sels[] = {\n+\t\"mmdc_ch0_axi\",\t \"pll3_usb_otg\", \"pll5_video_div\",\n+\t\"pll2_pfd0_352m\", \"pll2_pfd2_396m\", \"pll3_pfd1_540m\",\n+};\n+static const char *const ipu1_di0_sels[] = {\n+\t\"ipu1_di0_pre\", \"dummy\", \"dummy\", \"ldb_di0\", \"ldb_di1\",\n+};\n+static const char *const ipu1_di1_sels[] = {\n+\t\"ipu1_di1_pre\", \"dummy\", \"dummy\", \"ldb_di0\", \"ldb_di1\",\n+};\n+static const char *const ipu2_di0_sels[] = {\n+\t\"ipu2_di0_pre\", \"dummy\", \"dummy\", \"ldb_di0\", \"ldb_di1\",\n+};\n+static const char *const ipu2_di1_sels[] = {\n+\t\"ipu2_di1_pre\", \"dummy\", \"dummy\", \"ldb_di0\", \"ldb_di1\",\n+};\n+static const char *ipu1_di0_sels_2[] = {\n+\t\"ipu1_di0_pre\", \"dummy\", \"dummy\", \"ldb_di0_podf\", \"ldb_di1_podf\",\n+};\n+static const char *ipu1_di1_sels_2[] = {\n+\t\"ipu1_di1_pre\", \"dummy\", \"dummy\", \"ldb_di0_podf\", \"ldb_di1_podf\",\n+};\n+static const char *ipu2_di0_sels_2[] = {\n+\t\"ipu2_di0_pre\", \"dummy\", \"dummy\", \"ldb_di0_podf\", \"ldb_di1_podf\",\n+};\n+static const char *ipu2_di1_sels_2[] = {\n+\t\"ipu2_di1_pre\", \"dummy\", \"dummy\", \"ldb_di0_podf\", \"ldb_di1_podf\",\n+};\n+\n+static unsigned int share_count_mipi_core_cfg;\n \n static int imx6q_clk_probe(struct udevice *dev)\n {\n@@ -69,15 +128,37 @@ static int imx6q_clk_probe(struct udevice *dev)\n \t\t\t base + 0x10, 0x3));\n \tclk_dm(IMX6QDL_CLK_PLL3_60M,\n \t imx_clk_fixed_factor(dev, \"pll3_60m\", \"pll3_usb_otg\", 1, 8));\n-\tclk_dm(IMX6QDL_CLK_PLL2_PFD0_352M,\n-\t imx_clk_pfd(\"pll2_pfd0_352m\", \"pll2_bus\", base + 0x100, 0));\n-\tclk_dm(IMX6QDL_CLK_PLL2_PFD2_396M,\n-\t imx_clk_pfd(\"pll2_pfd2_396m\", \"pll2_bus\", base + 0x100, 2));\n+\tclk_dm(IMX6QDL_CLK_PLL3_80M,\n+\t imx_clk_fixed_factor(dev, \"pll3_80m\", \"pll3_usb_otg\", 1, 6));\n+\tclk_dm(IMX6QDL_CLK_PLL3_120M,\n+\t imx_clk_fixed_factor(dev, \"pll3_120m\", \"pll3_usb_otg\", 1, 4));\n+\tclk_dm(IMX6QDL_CLK_PLL5, imx_clk_pllv3(dev, IMX_PLLV3_AV, \"pll5\", \"osc\",\n+\t\t\t\t\t base + 0xa0, 0x7f));\n+\tclk_dm(IMX6QDL_CLK_PLL5_VIDEO,\n+\t imx_clk_gate(dev, \"pll5_video\", \"pll5\", base + 0xa0, 13));\n \tclk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, \"pll6\",\n \t\t\t\t\t \"osc\", base + 0xe0, 0x3));\n \tclk_dm(IMX6QDL_CLK_PLL6_ENET,\n \t imx_clk_gate(dev, \"pll6_enet\", \"pll6\", base + 0xe0, 13));\n \n+\tclk_dm(IMX6QDL_CLK_PLL2_PFD0_352M,\n+\t imx_clk_pfd(\"pll2_pfd0_352m\", \"pll2_bus\", base + 0x100, 0));\n+\tclk_dm(IMX6QDL_CLK_PLL2_PFD2_396M,\n+\t imx_clk_pfd(\"pll2_pfd2_396m\", \"pll2_bus\", base + 0x100, 2));\n+\tclk_dm(IMX6QDL_CLK_PLL3_PFD1_540M,\n+\t imx_clk_pfd(\"pll3_pfd1_540m\", \"pll3_usb_otg\", base + 0xf0, 1));\n+\n+\tclk_dm(IMX6QDL_CLK_PLL2_198M,\n+\t imx_clk_fixed_factor(dev, \"pll2_198m\", \"pll2_pfd2_396m\", 1, 2));\n+\tclk_dm(IMX6QDL_CLK_PLL5_POST_DIV,\n+\t imx_clk_fixed_factor(dev, \"pll5_post_div\", \"pll5_video\", 1, 1));\n+\tclk_dm(IMX6QDL_CLK_PLL5_VIDEO_DIV,\n+\t imx_clk_fixed_factor(dev, \"pll5_video_div\", \"pll5_post_div\", 1,\n+\t\t\t\t 1));\n+\tclk_dm(IMX6QDL_CLK_VIDEO_27M,\n+\t imx_clk_fixed_factor(dev, \"video_27m\", \"pll3_pfd1_540m\", 1,\n+\t\t\t\t 20));\n+\n \t/* CCM clocks */\n \tbase = dev_read_addr_ptr(dev);\n \tif (!base)\n@@ -105,6 +186,19 @@ static int imx6q_clk_probe(struct udevice *dev)\n \t\t\t\t ecspi_sels, ARRAY_SIZE(ecspi_sels)));\n \t}\n \n+\tclk_dm(IMX6QDL_CLK_PERIPH_PRE,\n+\t imx_clk_mux(dev, \"periph_pre\", base + 0x18, 18, 2,\n+\t\t\t periph_pre_sels, ARRAY_SIZE(periph_pre_sels)));\n+\tclk_dm(IMX6QDL_CLK_PERIPH2_PRE,\n+\t imx_clk_mux(dev, \"periph2_pre\", base + 0x18, 21, 2,\n+\t\t\t periph_pre_sels, ARRAY_SIZE(periph_pre_sels)));\n+\tclk_dm(IMX6QDL_CLK_PERIPH,\n+\t imx_clk_busy_mux(dev, \"periph\", base + 0x14, 25, 1, base + 0x48,\n+\t\t\t\t5, periph_sels, ARRAY_SIZE(periph_sels)));\n+\tclk_dm(IMX6QDL_CLK_PERIPH2,\n+\t imx_clk_busy_mux(dev, \"periph2\", base + 0x14, 26, 1, base + 0x48,\n+\t\t\t\t3, periph2_sels, ARRAY_SIZE(periph2_sels)));\n+\n \tclk_dm(IMX6QDL_CLK_USDHC1_PODF,\n \t imx_clk_divider(dev, \"usdhc1_podf\", \"usdhc1_sel\", base + 0x24,\n \t\t\t 11, 3));\n@@ -134,6 +228,192 @@ static int imx6q_clk_probe(struct udevice *dev)\n \t\t\t\t base + 0x38, 19, 6));\n \t}\n \n+\tclk_dm(IMX6QDL_CLK_AHB,\n+\t imx_clk_busy_divider(dev, \"ahb\", \"periph\", base + 0x14, 10, 3,\n+\t\t\t\t base + 0x48, 1));\n+\tclk_dm(IMX6QDL_CLK_IPG,\n+\t imx_clk_divider(dev, \"ipg\", \"ahb\", base + 0x14, 8, 2));\n+\tclk_dm(IMX6QDL_CLK_IPG_PER,\n+\t imx_clk_divider(dev, \"ipg_per\", \"ipg\", base + 0x1c, 0, 6));\n+\tclk_dm(IMX6QDL_CLK_UART_IPG,\n+\t imx_clk_gate2(dev, \"uart_ipg\", \"ipg\", base + 0x7c, 24));\n+\n+\tif (of_machine_is_compatible(\"fsl,imx6qp\")) {\n+\t\tclk_dm(IMX6QDL_CLK_MMDC_CH1_AXI_CG,\n+\t\t imx_clk_gate2(dev, \"mmdc_ch1_axi_cg\", \"periph2\",\n+\t\t\t\t base + 0x4, 18));\n+\t\tclk_dm(IMX6QDL_CLK_MMDC_CH1_AXI_PODF,\n+\t\t imx_clk_busy_divider(dev, \"mmdc_ch1_axi_podf\",\n+\t\t\t\t\t \"mmdc_ch1_axi_cg\", base + 0x14, 3,\n+\t\t\t\t\t 3, base + 0x48, 2));\n+\t} else {\n+\t\tclk_dm(IMX6QDL_CLK_MMDC_CH1_AXI_PODF,\n+\t\t imx_clk_busy_divider(dev, \"mmdc_ch1_axi_podf\", \"periph2\",\n+\t\t\t\t\t base + 0x14, 3, 3, base + 0x48, 2));\n+\t}\n+\n+\tclk_dm(IMX6QDL_CLK_MMDC_CH0_AXI_PODF,\n+\t imx_clk_busy_divider(dev, \"mmdc_ch0_axi_podf\", \"periph\",\n+\t\t\t\t base + 0x14, 19, 3, base + 0x48, 4));\n+\n+\tclk_dm(IMX6QDL_CLK_MMDC_CH0_AXI,\n+\t imx_clk_gate2_flags(dev, \"mmdc_ch0_axi\", \"mmdc_ch0_axi_podf\",\n+\t\t\t\t base + 0x74, 20, CLK_IS_CRITICAL));\n+\tclk_dm(IMX6QDL_CLK_MMDC_CH1_AXI,\n+\t imx_clk_gate2(dev, \"mmdc_ch1_axi\", \"mmdc_ch1_axi_podf\",\n+\t\t\t base + 0x74, 22));\n+\n+\tclk_dm(IMX6QDL_CLK_IPU1_SEL,\n+\t imx_clk_mux(dev, \"ipu1_sel\", base + 0x3c, 9, 2, ipu_sels,\n+\t\t\t ARRAY_SIZE(ipu_sels)));\n+\tclk_dm(IMX6QDL_CLK_IPU2_SEL,\n+\t imx_clk_mux(dev, \"ipu2_sel\", base + 0x3c, 14, 2, ipu_sels,\n+\t\t\t ARRAY_SIZE(ipu_sels)));\n+\n+\tif (of_machine_is_compatible(\"fsl,imx6qp\")) {\n+\t\tclk_dm(IMX6QDL_CLK_LDB_DI0_SEL,\n+\t\t imx_clk_mux(dev, \"ldb_di0_sel\", base + 0x2c, 9, 3,\n+\t\t\t\t ldb_di_sels, ARRAY_SIZE(ldb_di_sels)));\n+\t\tclk_dm(IMX6QDL_CLK_LDB_DI1_SEL,\n+\t\t imx_clk_mux(dev, \"ldb_di1_sel\", base + 0x2c, 12, 3,\n+\t\t\t\t ldb_di_sels, ARRAY_SIZE(ldb_di_sels)));\n+\t} else {\n+\t\t/*\n+ * Need to set these as read-only due to a hardware bug.\n+ * Keeping default mux values. Fixed on the i.MX6 QuadPlus\n+ */\n+\t\tclk_dm(IMX6QDL_CLK_LDB_DI0_SEL,\n+\t\t imx_clk_mux_flags(dev, \"ldb_di0_sel\", base + 0x2c, 9, 3,\n+\t\t\t\t\t ldb_di_sels, ARRAY_SIZE(ldb_di_sels),\n+\t\t\t\t\t CLK_SET_RATE_PARENT |\n+\t\t\t\t\t\t CLK_MUX_READ_ONLY));\n+\t\tclk_dm(IMX6QDL_CLK_LDB_DI1_SEL,\n+\t\t imx_clk_mux_flags(dev, \"ldb_di1_sel\", base + 0x2c, 12, 3,\n+\t\t\t\t\t ldb_di_sels, ARRAY_SIZE(ldb_di_sels),\n+\t\t\t\t\t CLK_SET_RATE_PARENT |\n+\t\t\t\t\t\t CLK_MUX_READ_ONLY));\n+\t}\n+\n+\tclk_dm(IMX6QDL_CLK_IPU1_DI0_PRE_SEL,\n+\t imx_clk_mux_flags(dev, \"ipu1_di0_pre_sel\", base + 0x34, 6, 3,\n+\t\t\t\t ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels),\n+\t\t\t\t CLK_SET_RATE_PARENT));\n+\tclk_dm(IMX6QDL_CLK_IPU1_DI1_PRE_SEL,\n+\t imx_clk_mux_flags(dev, \"ipu1_di1_pre_sel\", base + 0x34, 15, 3,\n+\t\t\t\t ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels),\n+\t\t\t\t CLK_SET_RATE_PARENT));\n+\tclk_dm(IMX6QDL_CLK_IPU2_DI0_PRE_SEL,\n+\t imx_clk_mux_flags(dev, \"ipu2_di0_pre_sel\", base + 0x38, 6, 3,\n+\t\t\t\t ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels),\n+\t\t\t\t CLK_SET_RATE_PARENT));\n+\tclk_dm(IMX6QDL_CLK_IPU2_DI1_PRE_SEL,\n+\t imx_clk_mux_flags(dev, \"ipu2_di1_pre_sel\", base + 0x38, 15, 3,\n+\t\t\t\t ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels),\n+\t\t\t\t CLK_SET_RATE_PARENT));\n+\n+\tif (of_machine_is_compatible(\"fsl,imx6qp\")) {\n+\t\tclk_dm(IMX6QDL_CLK_LDB_DI0,\n+\t\t imx_clk_gate2(dev, \"ldb_di0\", \"ldb_di0_sel\", base + 0x74,\n+\t\t\t\t 12));\n+\t\tclk_dm(IMX6QDL_CLK_LDB_DI1,\n+\t\t imx_clk_gate2(dev, \"ldb_di1\", \"ldb_di1_sel\", base + 0x74,\n+\t\t\t\t 14));\n+\t\tclk_dm(IMX6QDL_CLK_LDB_DI0_DIV_3_5,\n+\t\t imx_clk_fixed_factor(dev, \"ldb_di0_div_3_5\", \"ldb_di0\",\n+\t\t\t\t\t 2, 7));\n+\t\tclk_dm(IMX6QDL_CLK_LDB_DI1_DIV_3_5,\n+\t\t imx_clk_fixed_factor(dev, \"ldb_di1_div_3_5\", \"ldb_di1\",\n+\t\t\t\t\t 2, 7));\n+\t\tclk_dm(IMX6QDL_CLK_LDB_DI0_PODF,\n+\t\t imx_clk_divider(dev, \"ldb_di0_podf\", \"ldb_di0_div_3_5\",\n+\t\t\t\t base + 0x20, 10, 1));\n+\t\tclk_dm(IMX6QDL_CLK_LDB_DI1_PODF,\n+\t\t imx_clk_divider(dev, \"ldb_di1_podf\", \"ldb_di1_div_3_5\",\n+\t\t\t\t base + 0x20, 11, 1));\n+\t} else {\n+\t\tclk_dm(IMX6QDL_CLK_LDB_DI0_DIV_3_5,\n+\t\t imx_clk_fixed_factor(dev, \"ldb_di0_div_3_5\",\n+\t\t\t\t\t \"ldb_di0_sel\", 2, 7));\n+\t\tclk_dm(IMX6QDL_CLK_LDB_DI1_DIV_3_5,\n+\t\t imx_clk_fixed_factor(dev, \"ldb_di1_div_3_5\",\n+\t\t\t\t\t \"ldb_di1_sel\", 2, 7));\n+\t\tclk_dm(IMX6QDL_CLK_LDB_DI0_PODF,\n+\t\t imx_clk_divider(dev, \"ldb_di0_podf\", \"ldb_di0_div_3_5\",\n+\t\t\t\t base + 0x20, 10, 1));\n+\t\tclk_dm(IMX6QDL_CLK_LDB_DI1_PODF,\n+\t\t imx_clk_divider(dev, \"ldb_di1_podf\", \"ldb_di1_div_3_5\",\n+\t\t\t\t base + 0x20, 11, 1));\n+\t\tclk_dm(IMX6QDL_CLK_LDB_DI0,\n+\t\t imx_clk_gate2(dev, \"ldb_di0\", \"ldb_di0_podf\",\n+\t\t\t\t base + 0x74, 12));\n+\t\tclk_dm(IMX6QDL_CLK_LDB_DI1,\n+\t\t imx_clk_gate2(dev, \"ldb_di1\", \"ldb_di1_podf\",\n+\t\t\t\t base + 0x74, 14));\n+\t}\n+\n+\tclk_dm(IMX6QDL_CLK_IPU1_PODF,\n+\t imx_clk_divider(dev, \"ipu1_podf\", \"ipu1_sel\", base + 0x3c, 11,\n+\t\t\t 3));\n+\tclk_dm(IMX6QDL_CLK_IPU2_PODF,\n+\t imx_clk_divider(dev, \"ipu2_podf\", \"ipu2_sel\", base + 0x3c, 16,\n+\t\t\t 3));\n+\tclk_dm(IMX6QDL_CLK_IPU1_DI0_PRE,\n+\t imx_clk_divider(dev, \"ipu1_di0_pre\", \"ipu1_di0_pre_sel\",\n+\t\t\t base + 0x34, 3, 3));\n+\tclk_dm(IMX6QDL_CLK_IPU1_DI1_PRE,\n+\t imx_clk_divider(dev, \"ipu1_di1_pre\", \"ipu1_di1_pre_sel\",\n+\t\t\t base + 0x34, 12, 3));\n+\tclk_dm(IMX6QDL_CLK_IPU2_DI0_PRE,\n+\t imx_clk_divider(dev, \"ipu2_di0_pre\", \"ipu2_di0_pre_sel\",\n+\t\t\t base + 0x38, 3, 3));\n+\tclk_dm(IMX6QDL_CLK_IPU2_DI1_PRE,\n+\t imx_clk_divider(dev, \"ipu2_di1_pre\", \"ipu2_di1_pre_sel\",\n+\t\t\t base + 0x38, 12, 3));\n+\n+\tif (of_machine_is_compatible(\"fsl,imx6qp\")) {\n+\t\tclk_dm(IMX6QDL_CLK_IPU1_DI0_SEL,\n+\t\t imx_clk_mux_flags(dev, \"ipu1_di0_sel\", base + 0x34, 0, 3,\n+\t\t\t\t\t ipu1_di0_sels_2,\n+\t\t\t\t\t ARRAY_SIZE(ipu1_di0_sels_2),\n+\t\t\t\t\t CLK_SET_RATE_PARENT));\n+\t\tclk_dm(IMX6QDL_CLK_IPU1_DI1_SEL,\n+\t\t imx_clk_mux_flags(dev, \"ipu1_di1_sel\", base + 0x34, 9, 3,\n+\t\t\t\t\t ipu1_di1_sels_2,\n+\t\t\t\t\t ARRAY_SIZE(ipu1_di1_sels_2),\n+\t\t\t\t\t CLK_SET_RATE_PARENT));\n+\t\tclk_dm(IMX6QDL_CLK_IPU2_DI0_SEL,\n+\t\t imx_clk_mux_flags(dev, \"ipu2_di0_sel\", base + 0x38, 0, 3,\n+\t\t\t\t\t ipu2_di0_sels_2,\n+\t\t\t\t\t ARRAY_SIZE(ipu2_di0_sels_2),\n+\t\t\t\t\t CLK_SET_RATE_PARENT));\n+\t\tclk_dm(IMX6QDL_CLK_IPU2_DI1_SEL,\n+\t\t imx_clk_mux_flags(dev, \"ipu2_di1_sel\", base + 0x38, 9, 3,\n+\t\t\t\t\t ipu2_di1_sels_2,\n+\t\t\t\t\t ARRAY_SIZE(ipu2_di1_sels_2),\n+\t\t\t\t\t CLK_SET_RATE_PARENT));\n+\t} else {\n+\t\tclk_dm(IMX6QDL_CLK_IPU1_DI0_SEL,\n+\t\t imx_clk_mux_flags(dev, \"ipu1_di0_sel\", base + 0x34, 0, 3,\n+\t\t\t\t\t ipu1_di0_sels,\n+\t\t\t\t\t ARRAY_SIZE(ipu1_di0_sels),\n+\t\t\t\t\t CLK_SET_RATE_PARENT));\n+\t\tclk_dm(IMX6QDL_CLK_IPU1_DI1_SEL,\n+\t\t imx_clk_mux_flags(dev, \"ipu1_di1_sel\", base + 0x34, 9, 3,\n+\t\t\t\t\t ipu1_di1_sels,\n+\t\t\t\t\t ARRAY_SIZE(ipu1_di1_sels),\n+\t\t\t\t\t CLK_SET_RATE_PARENT));\n+\t\tclk_dm(IMX6QDL_CLK_IPU2_DI0_SEL,\n+\t\t imx_clk_mux_flags(dev, \"ipu2_di0_sel\", base + 0x38, 0, 3,\n+\t\t\t\t\t ipu2_di0_sels,\n+\t\t\t\t\t ARRAY_SIZE(ipu2_di0_sels),\n+\t\t\t\t\t CLK_SET_RATE_PARENT));\n+\t\tclk_dm(IMX6QDL_CLK_IPU2_DI1_SEL,\n+\t\t imx_clk_mux_flags(dev, \"ipu2_di1_sel\", base + 0x38, 9, 3,\n+\t\t\t\t\t ipu2_di1_sels,\n+\t\t\t\t\t ARRAY_SIZE(ipu2_di1_sels),\n+\t\t\t\t\t CLK_SET_RATE_PARENT));\n+\t}\n+\n \tclk_dm(IMX6QDL_CLK_ECSPI1,\n \t imx_clk_gate2(dev, \"ecspi1\", \"ecspi_root\", base + 0x6c, 0));\n \tclk_dm(IMX6QDL_CLK_ECSPI2,\n@@ -142,11 +422,11 @@ static int imx6q_clk_probe(struct udevice *dev)\n \t imx_clk_gate2(dev, \"ecspi3\", \"ecspi_root\", base + 0x6c, 4));\n \tclk_dm(IMX6QDL_CLK_ECSPI4,\n \t imx_clk_gate2(dev, \"ecspi4\", \"ecspi_root\", base + 0x6c, 6));\n-\tclk_dm(IMX6QDL_CLK_UART_IPG,\n-\t imx_clk_gate2(dev, \"uart_ipg\", \"ipg\", base + 0x7c, 24));\n \tclk_dm(IMX6QDL_CLK_UART_SERIAL,\n \t imx_clk_gate2(dev, \"uart_serial\", \"uart_serial_podf\",\n \t\t\t base + 0x7c, 26));\n+\tclk_dm(IMX6QDL_CLK_USBOH3,\n+\t imx_clk_gate2(dev, \"usboh3\", \"ipg\", base + 0x80, 0));\n \tclk_dm(IMX6QDL_CLK_USDHC1,\n \t imx_clk_gate2(dev, \"usdhc1\", \"usdhc1_podf\", base + 0x80, 2));\n \tclk_dm(IMX6QDL_CLK_USDHC2,\n@@ -155,20 +435,6 @@ static int imx6q_clk_probe(struct udevice *dev)\n \t imx_clk_gate2(dev, \"usdhc3\", \"usdhc3_podf\", base + 0x80, 6));\n \tclk_dm(IMX6QDL_CLK_USDHC4,\n \t imx_clk_gate2(dev, \"usdhc4\", \"usdhc4_podf\", base + 0x80, 8));\n-\n-\tclk_dm(IMX6QDL_CLK_PERIPH_PRE,\n-\t imx_clk_mux(dev, \"periph_pre\", base + 0x18, 18, 2,\n-\t\t\t periph_pre_sels, ARRAY_SIZE(periph_pre_sels)));\n-\tclk_dm(IMX6QDL_CLK_PERIPH,\n-\t imx_clk_busy_mux(dev, \"periph\", base + 0x14, 25, 1, base + 0x48,\n-\t\t\t\t5, periph_sels, ARRAY_SIZE(periph_sels)));\n-\tclk_dm(IMX6QDL_CLK_AHB,\n-\t imx_clk_busy_divider(dev, \"ahb\", \"periph\", base + 0x14, 10, 3,\n-\t\t\t\t base + 0x48, 1));\n-\tclk_dm(IMX6QDL_CLK_IPG,\n-\t imx_clk_divider(dev, \"ipg\", \"ahb\", base + 0x14, 8, 2));\n-\tclk_dm(IMX6QDL_CLK_IPG_PER,\n-\t imx_clk_divider(dev, \"ipg_per\", \"ipg\", base + 0x1c, 0, 6));\n \tclk_dm(IMX6QDL_CLK_I2C1,\n \t imx_clk_gate2(dev, \"i2c1\", \"ipg_per\", base + 0x70, 6));\n \tclk_dm(IMX6QDL_CLK_I2C2,\n@@ -183,11 +449,37 @@ static int imx6q_clk_probe(struct udevice *dev)\n \t imx_clk_gate2(dev, \"pwm3\", \"ipg_per\", base + 0x78, 20));\n \tclk_dm(IMX6QDL_CLK_PWM4,\n \t imx_clk_gate2(dev, \"pwm4\", \"ipg_per\", base + 0x78, 22));\n-\n \tclk_dm(IMX6QDL_CLK_ENET,\n \t imx_clk_gate2(dev, \"enet\", \"ipg\", base + 0x6c, 10));\n \tclk_dm(IMX6QDL_CLK_ENET_REF,\n \t imx_clk_fixed_factor(dev, \"enet_ref\", \"pll6_enet\", 1, 1));\n+\tclk_dm(IMX6QDL_CLK_MIPI_CORE_CFG,\n+\t imx_clk_gate2_shared(dev, \"mipi_core_cfg\", \"video_27m\",\n+\t\t\t\t base + 0x74, 16,\n+\t\t\t\t &share_count_mipi_core_cfg));\n+\tclk_dm(IMX6QDL_CLK_HDMI_IAHB,\n+\t imx_clk_gate2(dev, \"hdmi_iahb\", \"ahb\", base + 0x70, 0));\n+\tclk_dm(IMX6QDL_CLK_HDMI_ISFR,\n+\t imx_clk_gate2(dev, \"hdmi_isfr\", \"mipi_core_cfg\", base + 0x70,\n+\t\t\t 4));\n+\tclk_dm(IMX6QDL_CLK_IPU1,\n+\t imx_clk_gate2(dev, \"ipu1\", \"ipu1_podf\", base + 0x74, 0));\n+\tclk_dm(IMX6QDL_CLK_IPU2,\n+\t imx_clk_gate2(dev, \"ipu2\", \"ipu2_podf\", base + 0x74, 6));\n+\tclk_dm(IMX6QDL_CLK_IPU1_DI0,\n+\t imx_clk_gate2(dev, \"ipu1_di0\", \"ipu1_di0_sel\", base + 0x74, 2));\n+\tclk_dm(IMX6QDL_CLK_IPU1_DI1,\n+\t imx_clk_gate2(dev, \"ipu1_di1\", \"ipu1_di1_sel\", base + 0x74, 4));\n+\tclk_dm(IMX6QDL_CLK_IPU2_DI0,\n+\t imx_clk_gate2(dev, \"ipu2_di0\", \"ipu2_di0_sel\", base + 0x74, 8));\n+\tclk_dm(IMX6QDL_CLK_IPU2_DI1,\n+\t imx_clk_gate2(dev, \"ipu2_di1\", \"ipu2_di1_sel\", base + 0x74, 10));\n+\n+\tif (of_machine_is_compatible(\"fsl,imx6dl\")) {\n+\t\tSET_CLK_RATE(IMX6QDL_CLK_PLL3_PFD1_540M, 540000000UL);\n+\t\tSET_CLK_PARENT(IMX6QDL_CLK_IPU1_SEL,\n+\t\t\t IMX6QDL_CLK_PLL3_PFD1_540M);\n+\t}\n \n \treturn 0;\n }\ndiff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h\nindex 7d14dbc395f..b53f35df84f 100644\n--- a/drivers/clk/imx/clk.h\n+++ b/drivers/clk/imx/clk.h\n@@ -95,6 +95,15 @@ static inline struct clk *imx_clk_gate2(struct udevice *dev, const char *name,\n \t\t\tshift, 0x3, 0, NULL);\n }\n \n+static inline struct clk *\n+imx_clk_gate2_flags(struct udevice *dev, const char *name, const char *parent,\n+\t\t void __iomem *reg, u8 shift, unsigned long flags)\n+{\n+\treturn clk_register_gate2(dev, name, parent,\n+\t\t\t\t flags | CLK_SET_RATE_PARENT, reg, shift, 0x3,\n+\t\t\t\t 0, NULL);\n+}\n+\n static inline struct clk *imx_clk_gate2_shared(struct udevice *dev, const char *name,\n \t\t\t\t\t const char *parent,\n \t\t\t\t\t void __iomem *reg, u8 shift,\n","prefixes":["v3","3/6"]}