{"id":2196335,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2196335/?format=json","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.0/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260213084956.1031000-3-brian.ruley@gehealthcare.com>","date":"2026-02-13T08:49:51","name":"[v3,2/6] clk: imx6q: apply clang-format","commit_ref":"3632346f4bcfb2b40505a382d166dcbcd5516760","pull_url":null,"state":"accepted","archived":false,"hash":"3c5be58271f5e16f34783be5c1a94d48bdeb3c43","submitter":{"id":89422,"url":"http://patchwork.ozlabs.org/api/1.0/people/89422/?format=json","name":"Brian Ruley","email":"brian.ruley@gehealthcare.com"},"delegate":{"id":151988,"url":"http://patchwork.ozlabs.org/api/1.0/users/151988/?format=json","username":"festevam","first_name":"Fabio","last_name":"Estevam","email":"festevam@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260213084956.1031000-3-brian.ruley@gehealthcare.com/mbox/","series":[{"id":492095,"url":"http://patchwork.ozlabs.org/api/1.0/series/492095/?format=json","date":"2026-02-13T08:49:49","name":"Enable the IPUv3 driver to use CCF","version":3,"mbox":"http://patchwork.ozlabs.org/series/492095/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2196335/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gehealthcare.com header.i=@gehealthcare.com\n header.a=rsa-sha256 header.s=selector1 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phobos.denx.de","X-Virus-Status":"Clean"},"content":"Reduces the number of checkpatch warnings in the following commits.\n\nSigned-off-by: Brian Ruley \n---\n\nChanges in v3:\n- Fix commit message\n\n drivers/clk/imx/clk-imx6q.c | 102 ++++++++++++++++++++++--------------\n 1 file changed, 62 insertions(+), 40 deletions(-)","diff":"diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c\nindex b69355cefc7..f11f9045abb 100644\n--- a/drivers/clk/imx/clk-imx6q.c\n+++ b/drivers/clk/imx/clk-imx6q.c\n@@ -31,12 +31,28 @@ static struct clk_ops imx6q_clk_ops = {\n \t.disable = ccf_clk_disable,\n };\n \n-static const char *const usdhc_sels[] = { \"pll2_pfd2_396m\", \"pll2_pfd0_352m\", };\n-static const char *const periph_sels[]\t= { \"periph_pre\", \"periph_clk2\", };\n-static const char *const periph_pre_sels[] = { \"pll2_bus\", \"pll2_pfd2_396m\",\n-\t\t\t\t\t \"pll2_pfd0_352m\", \"pll2_198m\", };\n-static const char *const uart_sels[] = { \"pll3_80m\", \"osc\", };\n-static const char *const ecspi_sels[] = { \"pll3_60m\", \"osc\", };\n+static const char *const usdhc_sels[] = {\n+\t\"pll2_pfd2_396m\",\n+\t\"pll2_pfd0_352m\",\n+};\n+static const char *const periph_sels[] = {\n+\t\"periph_pre\",\n+\t\"periph_clk2\",\n+};\n+static const char *const periph_pre_sels[] = {\n+\t\"pll2_bus\",\n+\t\"pll2_pfd2_396m\",\n+\t\"pll2_pfd0_352m\",\n+\t\"pll2_198m\",\n+};\n+static const char *const uart_sels[] = {\n+\t\"pll3_80m\",\n+\t\"osc\",\n+};\n+static const char *const ecspi_sels[] = {\n+\t\"pll3_60m\",\n+\t\"osc\",\n+};\n \n static int imx6q_clk_probe(struct udevice *dev)\n {\n@@ -52,13 +68,13 @@ static int imx6q_clk_probe(struct udevice *dev)\n \t imx_clk_pllv3(dev, IMX_PLLV3_USB, \"pll3_usb_otg\", \"osc\",\n \t\t\t base + 0x10, 0x3));\n \tclk_dm(IMX6QDL_CLK_PLL3_60M,\n-\t imx_clk_fixed_factor(dev, \"pll3_60m\", \"pll3_usb_otg\", 1, 8));\n+\t imx_clk_fixed_factor(dev, \"pll3_60m\", \"pll3_usb_otg\", 1, 8));\n \tclk_dm(IMX6QDL_CLK_PLL2_PFD0_352M,\n \t imx_clk_pfd(\"pll2_pfd0_352m\", \"pll2_bus\", base + 0x100, 0));\n \tclk_dm(IMX6QDL_CLK_PLL2_PFD2_396M,\n \t imx_clk_pfd(\"pll2_pfd2_396m\", \"pll2_bus\", base + 0x100, 2));\n-\tclk_dm(IMX6QDL_CLK_PLL6,\n-\t imx_clk_pllv3(dev, IMX_PLLV3_ENET, \"pll6\", \"osc\", base + 0xe0, 0x3));\n+\tclk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, \"pll6\",\n+\t\t\t\t\t \"osc\", base + 0xe0, 0x3));\n \tclk_dm(IMX6QDL_CLK_PLL6_ENET,\n \t imx_clk_gate(dev, \"pll6_enet\", \"pll6\", base + 0xe0, 13));\n \n@@ -68,50 +84,54 @@ static int imx6q_clk_probe(struct udevice *dev)\n \t\treturn -EINVAL;\n \n \tclk_dm(IMX6QDL_CLK_USDHC1_SEL,\n-\t imx_clk_mux(dev, \"usdhc1_sel\", base + 0x1c, 16, 1,\n-\t\t\t usdhc_sels, ARRAY_SIZE(usdhc_sels)));\n+\t imx_clk_mux(dev, \"usdhc1_sel\", base + 0x1c, 16, 1, usdhc_sels,\n+\t\t\t ARRAY_SIZE(usdhc_sels)));\n \tclk_dm(IMX6QDL_CLK_USDHC2_SEL,\n-\t imx_clk_mux(dev, \"usdhc2_sel\", base + 0x1c, 17, 1,\n-\t\t\t usdhc_sels, ARRAY_SIZE(usdhc_sels)));\n+\t imx_clk_mux(dev, \"usdhc2_sel\", base + 0x1c, 17, 1, usdhc_sels,\n+\t\t\t ARRAY_SIZE(usdhc_sels)));\n \tclk_dm(IMX6QDL_CLK_USDHC3_SEL,\n-\t imx_clk_mux(dev, \"usdhc3_sel\", base + 0x1c, 18, 1,\n-\t\t\t usdhc_sels, ARRAY_SIZE(usdhc_sels)));\n+\t imx_clk_mux(dev, \"usdhc3_sel\", base + 0x1c, 18, 1, usdhc_sels,\n+\t\t\t ARRAY_SIZE(usdhc_sels)));\n \tclk_dm(IMX6QDL_CLK_USDHC4_SEL,\n-\t imx_clk_mux(dev, \"usdhc4_sel\", base + 0x1c, 19, 1,\n-\t\t\t usdhc_sels, ARRAY_SIZE(usdhc_sels)));\n+\t imx_clk_mux(dev, \"usdhc4_sel\", base + 0x1c, 19, 1, usdhc_sels,\n+\t\t\t ARRAY_SIZE(usdhc_sels)));\n \n \tif (of_machine_is_compatible(\"fsl,imx6qp\")) {\n \t\tclk_dm(IMX6QDL_CLK_UART_SEL,\n-\t\t imx_clk_mux(dev, \"uart_sel\", base + 0x24, 6, 1, uart_sels,\n-\t\t\t\t ARRAY_SIZE(uart_sels)));\n+\t\t imx_clk_mux(dev, \"uart_sel\", base + 0x24, 6, 1,\n+\t\t\t\t uart_sels, ARRAY_SIZE(uart_sels)));\n \t\tclk_dm(IMX6QDL_CLK_ECSPI_SEL,\n-\t\t imx_clk_mux(dev, \"ecspi_sel\", base + 0x38, 18, 1, ecspi_sels,\n-\t\t\t\t ARRAY_SIZE(ecspi_sels)));\n+\t\t imx_clk_mux(dev, \"ecspi_sel\", base + 0x38, 18, 1,\n+\t\t\t\t ecspi_sels, ARRAY_SIZE(ecspi_sels)));\n \t}\n \n \tclk_dm(IMX6QDL_CLK_USDHC1_PODF,\n-\t imx_clk_divider(dev, \"usdhc1_podf\", \"usdhc1_sel\",\n-\t\t\t base + 0x24, 11, 3));\n+\t imx_clk_divider(dev, \"usdhc1_podf\", \"usdhc1_sel\", base + 0x24,\n+\t\t\t 11, 3));\n \tclk_dm(IMX6QDL_CLK_USDHC2_PODF,\n-\t imx_clk_divider(dev, \"usdhc2_podf\", \"usdhc2_sel\",\n-\t\t\t base + 0x24, 16, 3));\n+\t imx_clk_divider(dev, \"usdhc2_podf\", \"usdhc2_sel\", base + 0x24,\n+\t\t\t 16, 3));\n \tclk_dm(IMX6QDL_CLK_USDHC3_PODF,\n-\t imx_clk_divider(dev, \"usdhc3_podf\", \"usdhc3_sel\",\n-\t\t\t base + 0x24, 19, 3));\n+\t imx_clk_divider(dev, \"usdhc3_podf\", \"usdhc3_sel\", base + 0x24,\n+\t\t\t 19, 3));\n \tclk_dm(IMX6QDL_CLK_USDHC4_PODF,\n-\t imx_clk_divider(dev, \"usdhc4_podf\", \"usdhc4_sel\",\n-\t\t\t base + 0x24, 22, 3));\n+\t imx_clk_divider(dev, \"usdhc4_podf\", \"usdhc4_sel\", base + 0x24,\n+\t\t\t 22, 3));\n \n \tif (of_machine_is_compatible(\"fsl,imx6qp\")) {\n \t\tclk_dm(IMX6QDL_CLK_UART_SERIAL_PODF,\n-\t\t imx_clk_divider(dev, \"uart_serial_podf\", \"uart_sel\", base + 0x24, 0, 6));\n+\t\t imx_clk_divider(dev, \"uart_serial_podf\", \"uart_sel\",\n+\t\t\t\t base + 0x24, 0, 6));\n \t\tclk_dm(IMX6QDL_CLK_ECSPI_ROOT,\n-\t\t imx_clk_divider(dev, \"ecspi_root\", \"ecspi_sel\", base + 0x38, 19, 6));\n+\t\t imx_clk_divider(dev, \"ecspi_root\", \"ecspi_sel\",\n+\t\t\t\t base + 0x38, 19, 6));\n \t} else {\n \t\tclk_dm(IMX6QDL_CLK_UART_SERIAL_PODF,\n-\t\t imx_clk_divider(dev, \"uart_serial_podf\", \"pll3_80m\", base + 0x24, 0, 6));\n+\t\t imx_clk_divider(dev, \"uart_serial_podf\", \"pll3_80m\",\n+\t\t\t\t base + 0x24, 0, 6));\n \t\tclk_dm(IMX6QDL_CLK_ECSPI_ROOT,\n-\t\t imx_clk_divider(dev, \"ecspi_root\", \"pll3_60m\", base + 0x38, 19, 6));\n+\t\t imx_clk_divider(dev, \"ecspi_root\", \"pll3_60m\",\n+\t\t\t\t base + 0x38, 19, 6));\n \t}\n \n \tclk_dm(IMX6QDL_CLK_ECSPI1,\n@@ -125,7 +145,8 @@ static int imx6q_clk_probe(struct udevice *dev)\n \tclk_dm(IMX6QDL_CLK_UART_IPG,\n \t imx_clk_gate2(dev, \"uart_ipg\", \"ipg\", base + 0x7c, 24));\n \tclk_dm(IMX6QDL_CLK_UART_SERIAL,\n-\t imx_clk_gate2(dev, \"uart_serial\", \"uart_serial_podf\", base + 0x7c, 26));\n+\t imx_clk_gate2(dev, \"uart_serial\", \"uart_serial_podf\",\n+\t\t\t base + 0x7c, 26));\n \tclk_dm(IMX6QDL_CLK_USDHC1,\n \t imx_clk_gate2(dev, \"usdhc1\", \"usdhc1_podf\", base + 0x80, 2));\n \tclk_dm(IMX6QDL_CLK_USDHC2,\n@@ -136,11 +157,11 @@ static int imx6q_clk_probe(struct udevice *dev)\n \t imx_clk_gate2(dev, \"usdhc4\", \"usdhc4_podf\", base + 0x80, 8));\n \n \tclk_dm(IMX6QDL_CLK_PERIPH_PRE,\n-\t imx_clk_mux(dev, \"periph_pre\", base + 0x18, 18, 2, periph_pre_sels,\n-\t\t\t ARRAY_SIZE(periph_pre_sels)));\n+\t imx_clk_mux(dev, \"periph_pre\", base + 0x18, 18, 2,\n+\t\t\t periph_pre_sels, ARRAY_SIZE(periph_pre_sels)));\n \tclk_dm(IMX6QDL_CLK_PERIPH,\n-\t imx_clk_busy_mux(dev, \"periph\", base + 0x14, 25, 1, base + 0x48,\n-\t\t\t\t5, periph_sels, ARRAY_SIZE(periph_sels)));\n+\t imx_clk_busy_mux(dev, \"periph\", base + 0x14, 25, 1, base + 0x48,\n+\t\t\t\t5, periph_sels, ARRAY_SIZE(periph_sels)));\n \tclk_dm(IMX6QDL_CLK_AHB,\n \t imx_clk_busy_divider(dev, \"ahb\", \"periph\", base + 0x14, 10, 3,\n \t\t\t\t base + 0x48, 1));\n@@ -163,7 +184,8 @@ static int imx6q_clk_probe(struct udevice *dev)\n \tclk_dm(IMX6QDL_CLK_PWM4,\n \t imx_clk_gate2(dev, \"pwm4\", \"ipg_per\", base + 0x78, 22));\n \n-\tclk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2(dev, \"enet\", \"ipg\", base + 0x6c, 10));\n+\tclk_dm(IMX6QDL_CLK_ENET,\n+\t imx_clk_gate2(dev, \"enet\", \"ipg\", base + 0x6c, 10));\n \tclk_dm(IMX6QDL_CLK_ENET_REF,\n \t imx_clk_fixed_factor(dev, \"enet_ref\", \"pll6_enet\", 1, 1));\n \n@@ -172,7 +194,7 @@ static int imx6q_clk_probe(struct udevice *dev)\n \n static const struct udevice_id imx6q_clk_ids[] = {\n \t{ .compatible = \"fsl,imx6q-ccm\" },\n-\t{ },\n+\t{},\n };\n \n U_BOOT_DRIVER(imx6q_clk) = {\n","prefixes":["v3","2/6"]}