{"id":2196290,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2196290/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260213103942.142823-4-skolothumtho@nvidia.com>","date":"2026-02-13T10:39:40","name":"[v6,3/5] hw/arm/smmuv3-accel: Allocate vEVENTQ for accelerated SMMUv3 devices","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"31529d80208deab51bc34f3ec6ff97cb2333d333","submitter":{"id":91580,"url":"http://patchwork.ozlabs.org/api/1.0/people/91580/?format=json","name":"Shameer Kolothum","email":"skolothumtho@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260213103942.142823-4-skolothumtho@nvidia.com/mbox/","series":[{"id":492079,"url":"http://patchwork.ozlabs.org/api/1.0/series/492079/?format=json","date":"2026-02-13T10:39:41","name":"vEVENTQ support for accelerated SMMUv3 devices","version":6,"mbox":"http://patchwork.ozlabs.org/series/492079/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2196290/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=YwvC0ITS;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fC81H3spJz1xr1\n\tfor ; Fri, 13 Feb 2026 21:44:19 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1vqqdz-00087i-0a; Fri, 13 Feb 2026 05:43:27 -0500","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1vqqdw-00086r-Rh; Fri, 13 Feb 2026 05:43:24 -0500","from\n mail-southcentralusazlp170120001.outbound.protection.outlook.com\n ([2a01:111:f403:c10d::1] helo=SN4PR2101CU001.outbound.protection.outlook.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1vqqdv-0006Xp-0Q; Fri, 13 Feb 2026 05:43:24 -0500","from BL1P223CA0031.NAMP223.PROD.OUTLOOK.COM (2603:10b6:208:5b6::6)\n by LV2PR12MB5726.namprd12.prod.outlook.com (2603:10b6:408:17e::9) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9611.11; Fri, 13 Feb\n 2026 10:43:15 +0000","from BL6PEPF0001AB4D.namprd04.prod.outlook.com\n (2603:10b6:208:5b6:cafe::50) by BL1P223CA0031.outlook.office365.com\n (2603:10b6:208:5b6::6) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9611.14 via Frontend Transport; Fri,\n 13 Feb 2026 10:43:29 +0000","from mail.nvidia.com (216.228.117.161) by\n BL6PEPF0001AB4D.mail.protection.outlook.com (10.167.242.71) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9611.8 via Frontend Transport; Fri, 13 Feb 2026 10:43:15 +0000","from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 13 Feb\n 2026 02:43:02 -0800","from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 13 Feb\n 2026 02:42:59 -0800"],"ARC-Seal":"i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=N/aSryUBa51W7aKJuKpcAU2qyj0UUDjsH67tjUvu6iFioGG+ayXHcz2SZEDpjz+IrOG1QUPBIvTqpiiY0obRBhuF5B6iD7fNTt25gGDwR3Z7VX/6iM+T3CQa//I/kGf92yj5a2GSf0Fdn3U6h+oLjr4oBuUA7inRrrV9Cj/p7o8B3k89YEfyrikjc84F89FuwutvGXBgdSQKRA/u6BGb/rRsPGTwPsrEVMMs88PQY7Q8Jmd/dmpN3+TsGkni1+1MIQ4EQEpfSdeWr8RXJl8WBSKuep5FQlH83XW2T8meFcDt8A1SHSVWcc17ZQJ3qBUXPtSROqkpJuKt2rfQw9K1Lg==","ARC-Message-Signature":"i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=lQqZ+dPQZapFThe2osR0f6IPTDtvq+hAOoI7ZZOijGU=;\n b=Sgh86yHq32QS1TCLo9CPqu6E3sidceiHfIOj4gWSoDy+H9U40J9TCPr+54SXZI2veL3M4GkFRjWeO8RG3NYS0sydzOgkBGZKLBR/8q3uwTpMew3hW2VQFzedpqx/n2jiMYDiBbmBgn1uGJSvCoOtWFhuXpYLpEeskumC/Bb5oAfOHTq1Je0v5kOdAsKkfdbxiZ5w346Iy57fNVmRDkty3x2/6PfBSQbf/t4nkvKBYDZDAED5Vwi2LTdzgxlzj0632aeHMOsBY233ivzBW4kXjx/ip8LOgzqStnbly5Q0oH3bd1Ur8vWlIp9mc6ThwBGsVFYVn3FXcWuMc74D7xDx4w==","ARC-Authentication-Results":"i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none (0)","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=lQqZ+dPQZapFThe2osR0f6IPTDtvq+hAOoI7ZZOijGU=;\n b=YwvC0ITSDQRhbtMRXdUhuF4Be6ot7EGUQqhiVxRfx8o4lQEFduRX7SQnMWeiFBOv3JjSCA/LWc8MptJu9+HifkOJrpk62ji5IuzF++XHDpwlL8rJpZ2hRd0BlsqM2RTNxZ5TbAf6N7hqWThjlzO0e07p4cJ8bD0hsU4mxiL8GOubRoYy8WHOzcuU15hI3jbhavw9jIRUQh39HU+7HZ1W/xh8IREcNBIcqvdBk9bIlhX57d8HRPorqdbzk9/DaljMboQUG7MbmP/kAG3iMxUos/Mreakegq7OlEOCB9PyYTrWYs0p6Lj6uqwZc4IlmanEpelzoKW5ZitYSgWTF+9c6w==","X-MS-Exchange-Authentication-Results":"spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;","Received-SPF":["Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C","permerror client-ip=2a01:111:f403:c10d::1;\n envelope-from=skolothumtho@nvidia.com;\n helo=SN4PR2101CU001.outbound.protection.outlook.com"],"From":"Shameer Kolothum ","To":", ","CC":", ,\n , , ,\n , , ,\n , , ,\n ","Subject":"[PATCH v6 3/5] hw/arm/smmuv3-accel: Allocate vEVENTQ for accelerated\n SMMUv3 devices","Date":"Fri, 13 Feb 2026 10:39:40 +0000","Message-ID":"<20260213103942.142823-4-skolothumtho@nvidia.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260213103942.142823-1-skolothumtho@nvidia.com>","References":"<20260213103942.142823-1-skolothumtho@nvidia.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-Originating-IP":"[10.126.230.35]","X-ClientProxiedBy":"rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"BL6PEPF0001AB4D:EE_|LV2PR12MB5726:EE_","X-MS-Office365-Filtering-Correlation-Id":"eb10c562-1f94-4456-5b1f-08de6aecb17b","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"BCL:0;\n ARA:13230040|82310400026|376014|1800799024|36860700013;","X-Microsoft-Antispam-Message-Info":"\n N3zqDgeltrDpZRtN+Cu+BDjyRWGizg4hf3hdFPMFwlG3K4yPJzftWCYlTe5DYo5sxpxuRPZuODWITBHFxueePVVFnZ8s3c6EXFetXx+rXy2jejLOvLwsfzJVfWnJMfuXOnM+MoYu/qrlEzgEPC5YSsZbI8BSaPKd3vEZhSuj9weOPZLhaTeNNgWIp+dtj8L1IfCfEp01HArqSwr4N9NGmPaC9JriqEGA5BxBujlz7ppvgh5/y4cpGyYtgUNfaFDNfLVU/kj1T3a1rNejyB7HOTjPfXqt3lrHBkwveTqGLGwZhLsphgV83rb8oLtZzjp0K9oo4e/JSkLyPcW2HdEnkA3leTQqPAsech9yU9x8DDYs4hjoFNVyr9e3fxg9iCkvRuJj0k02QY2GkCp9w/H3i4KoWePH5QYS+YUofQkIENCPBqTAppsWpg9djHCIw8JmkLeql2hpOqV5VlpIAHu5JI4Cq1+Lvl1FHpfW3TU8HB9WdhoZGx30/lmBiqo0yXCV+LNxcKy84IWpHkng6XK3XuJ7VZBEe9S2T4vcjs4OEVYnQBLjkFPYGjGW1SlGORqyREYYRObZk00rUbUewUy8pBoFZCYHb+JJlgELSBMIu0xiMV1hARPMPtimrgIMqDta7WCsLTFa/3wONgGhm2lblLugoDteb//xz+0Gilsa+1yySpeNmgETDTUleN1gtDHyPpByyJGg9G37T325xMVwWIKr2UYQj4ncsAQycp54V2DMAE2w2XMUePpIRF9tZq7XrN1iMoYrHEuR3oD05hEbgaPzLf2sQ8QWrRwppYA/+0982KvCwzht3TpLEj/xPRIcUNRUk3pamzpfLAsS+cBWhPwqMMHnkU6pxduQbxNV6cCyuz15DyYZFm+vcW2Sn3OT2IZQyoFVQPLP3mlAWql7beIA/ezq12VqNLt0vSPCMZbl+IL0LJ52Ok/3KllBKyjiRFAa+rObEnAUkC1Nkl0qKGH6R9/ht4T47FEK8pAv31UN+jPWC8RlWzij9mtPTiG3yv3EkVDZ9KCW9wJEIgafN+qMcN7VIOA5+GbAnfkNeAlde+zr5WdQUXrh6h8DcwgFiFHBFr+a2EjmSjKShTjPi+3X3wvW90hjr098lWVVNvNf/hmbucKUpQeYYxzRWEWxOiqURcS7dlwyMJ7nEN+6TcRdjea4GzNUj2fzFRfozqHBZw2VVb3pNNTqluoBj5Aw4/fwOohO/ts3n7lJiG5eDDx7fAwe0LYDO5W3OJpmPzsTjU7LIHj7pm5AYGaEE8DjoFSy5xibGoOSx1euzovzakfQZxT8/7Kq0Z7L276xhBCdxUBJzJnropgZJFRKrYAa0qpl5/Tsu4PyDSRKt69ipl14k0KhvVTbEQ6oTtIugk//f602VlrmN/4ZqEOwR3xKnLoHzsVLoRn3+CX9lbxxZRclkEbYiJaGkLb1mDm7wx9MTxWzQqgzfrpxNnBK0XcK68Y9iWdIxawq2ALuKbdwoeXTh+37yZHGOaMXbjg0dkA5ACSfvMTznnT69IUcfoz6xEwH3eztFCvMmKDM/9MFvLa7iyPyte8fdSR2jAaacJyxZsN7XHbOnrGJNA1GK8AXurE8dW4f+EhgNyO3wHYmpoCCmaS/jRlYsSZWB3syeawgiJrlWkdvH+3nG8tBrroyYIBb6uUjWhIDCPsE6D4kqg==","X-Forefront-Antispam-Report":"CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013); DIR:OUT;\n SFP:1101;","X-MS-Exchange-AntiSpam-MessageData-ChunkCount":"1","X-MS-Exchange-AntiSpam-MessageData-0":"\n UeyRz8vPUcRRrDeNd7YC6/RTMQG5seVQSFY2wGkOSg1MFl1eT4zv7rGDYQPfIzGVnH763/H1yY5/TWbj5uHviZIDRGQ0dlKA1H6SxlaWhhD6YBTEYUicXyTrtwxi7L+dzQjZJ3xm+sh7deZRDqDUkZKU6lNfFRWDkRRkrmTKlUqZZGUbZI2+IV4lBQ+RX936g5Ip25EMxs+jv6H9blDCJJ5muVl/1lhEVzin6hzGJAuGbXAeLP9fSssN749qaNbOwiNv4ZeKp1hDgahVze846x3B3hIPAo4ecHanWK09nOeJJESy+kGla0kdzZ12grAew1fVFk5EiISAbvOUiO4lelQ526eGzpPaiI8vmiCPuDvxePjCCGqDI6zPwhjiL5I2vda4jqzgFT6btBRnDAR2mLbElV/6/NbffvFTB0sXeUETanLW6ktyZHNo4hnF4kum","X-OriginatorOrg":"Nvidia.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"13 Feb 2026 10:43:15.3358 (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n eb10c562-1f94-4456-5b1f-08de6aecb17b","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n BL6PEPF0001AB4D.namprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"LV2PR12MB5726","X-Spam_score_int":"-10","X-Spam_score":"-1.1","X-Spam_bar":"-","X-Spam_report":"(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Nicolin Chen \n\nWhen the guest enables the Event Queue and a vIOMMU is present, allocate a\nvEVENTQ object so that host-side events related to the vIOMMU can be\nreceived and propagated back to the guest.\n\nFor cold-plugged devices using SMMUv3 acceleration, the vIOMMU is created\nbefore the guest boots. In this case, the vEVENTQ is allocated when the\nguest writes to SMMU_CR0 and sets EVENTQEN = 1.\n\nIf no cold-plugged device exists at boot (i.e. no vIOMMU initially), the\nvEVENTQ is allocated when a vIOMMU is created, i.e. during the first\ndevice hot-plug.\n\nAlso, rename the local error variable and refactor smmu_writel() to use\na single error accumulator with error_propagate().\n\nEvent read and propagation will be added in a later patch.\n\nSigned-off-by: Nicolin Chen \nTested-by: Nicolin Chen \nReviewed-by: Eric Auger \nSigned-off-by: Shameer Kolothum \n---\n hw/arm/smmuv3-accel.c | 61 +++++++++++++++++++++++++++++++++++++++++--\n hw/arm/smmuv3-accel.h | 6 +++++\n hw/arm/smmuv3.c | 17 +++++++-----\n 3 files changed, 75 insertions(+), 9 deletions(-)","diff":"diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex c19c526fca..d92fcb1a89 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -390,6 +390,19 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *bs, void *cmd, SMMUDevice *sdev,\n sizeof(Cmd), &entry_num, cmd, errp);\n }\n \n+static void smmuv3_accel_free_veventq(SMMUv3AccelState *accel)\n+{\n+ IOMMUFDVeventq *veventq = accel->veventq;\n+\n+ if (!veventq) {\n+ return;\n+ }\n+ close(veventq->veventq_fd);\n+ iommufd_backend_free_id(accel->viommu->iommufd, veventq->veventq_id);\n+ g_free(veventq);\n+ accel->veventq = NULL;\n+}\n+\n static void smmuv3_accel_free_viommu(SMMUv3AccelState *accel)\n {\n IOMMUFDViommu *viommu = accel->viommu;\n@@ -397,6 +410,7 @@ static void smmuv3_accel_free_viommu(SMMUv3AccelState *accel)\n if (!viommu) {\n return;\n }\n+ smmuv3_accel_free_veventq(accel);\n iommufd_backend_free_id(viommu->iommufd, accel->bypass_hwpt_id);\n iommufd_backend_free_id(viommu->iommufd, accel->abort_hwpt_id);\n iommufd_backend_free_id(viommu->iommufd, accel->viommu->viommu_id);\n@@ -404,6 +418,41 @@ static void smmuv3_accel_free_viommu(SMMUv3AccelState *accel)\n accel->viommu = NULL;\n }\n \n+bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp)\n+{\n+ SMMUv3AccelState *accel = s->s_accel;\n+ IOMMUFDVeventq *veventq;\n+ uint32_t veventq_id;\n+ uint32_t veventq_fd;\n+\n+ if (!accel || !accel->viommu) {\n+ return true;\n+ }\n+\n+ if (accel->veventq) {\n+ return true;\n+ }\n+\n+ if (!smmuv3_eventq_enabled(s)) {\n+ return true;\n+ }\n+\n+ if (!iommufd_backend_alloc_veventq(accel->viommu->iommufd,\n+ accel->viommu->viommu_id,\n+ IOMMU_VEVENTQ_TYPE_ARM_SMMUV3,\n+ 1 << s->eventq.log2size, &veventq_id,\n+ &veventq_fd, errp)) {\n+ return false;\n+ }\n+\n+ veventq = g_new(IOMMUFDVeventq, 1);\n+ veventq->veventq_id = veventq_id;\n+ veventq->veventq_fd = veventq_fd;\n+ veventq->viommu = accel->viommu;\n+ accel->veventq = veventq;\n+ return true;\n+}\n+\n static bool\n smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n Error **errp)\n@@ -429,6 +478,7 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n viommu->viommu_id = viommu_id;\n viommu->s2_hwpt_id = s2_hwpt_id;\n viommu->iommufd = idev->iommufd;\n+ accel->viommu = viommu;\n \n /*\n * Pre-allocate HWPTs for S1 bypass and abort cases. These will be attached\n@@ -448,14 +498,20 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n goto free_abort_hwpt;\n }\n \n+ /* Allocate a vEVENTQ if guest has enabled event queue */\n+ if (!smmuv3_accel_alloc_veventq(s, errp)) {\n+ goto free_bypass_hwpt;\n+ }\n+\n /* Attach a HWPT based on SMMUv3 GBPA.ABORT value */\n hwpt_id = smmuv3_accel_gbpa_hwpt(s, accel);\n if (!host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp)) {\n- goto free_bypass_hwpt;\n+ goto free_veventq;\n }\n- accel->viommu = viommu;\n return true;\n \n+free_veventq:\n+ smmuv3_accel_free_veventq(accel);\n free_bypass_hwpt:\n iommufd_backend_free_id(idev->iommufd, accel->bypass_hwpt_id);\n free_abort_hwpt:\n@@ -463,6 +519,7 @@ free_abort_hwpt:\n free_viommu:\n iommufd_backend_free_id(idev->iommufd, viommu->viommu_id);\n g_free(viommu);\n+ accel->viommu = NULL;\n return false;\n }\n \ndiff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h\nindex a8a64802ec..dba6c71de5 100644\n--- a/hw/arm/smmuv3-accel.h\n+++ b/hw/arm/smmuv3-accel.h\n@@ -22,6 +22,7 @@\n */\n typedef struct SMMUv3AccelState {\n IOMMUFDViommu *viommu;\n+ IOMMUFDVeventq *veventq;\n uint32_t bypass_hwpt_id;\n uint32_t abort_hwpt_id;\n QLIST_HEAD(, SMMUv3AccelDevice) device_list;\n@@ -50,6 +51,7 @@ bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error **errp);\n bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sdev,\n Error **errp);\n void smmuv3_accel_idr_override(SMMUv3State *s);\n+bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp);\n void smmuv3_accel_reset(SMMUv3State *s);\n #else\n static inline void smmuv3_accel_init(SMMUv3State *s)\n@@ -80,6 +82,10 @@ smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sdev,\n static inline void smmuv3_accel_idr_override(SMMUv3State *s)\n {\n }\n+static inline bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp)\n+{\n+ return true;\n+}\n static inline void smmuv3_accel_reset(SMMUv3State *s)\n {\n }\ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex c08d58c579..f804d3af25 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -1597,14 +1597,17 @@ static MemTxResult smmu_writell(SMMUv3State *s, hwaddr offset,\n static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,\n uint64_t data, MemTxAttrs attrs)\n {\n- Error *local_err = NULL;\n+ Error *err = NULL, *local_err = NULL;\n \n switch (offset) {\n case A_CR0:\n s->cr[0] = data;\n s->cr0ack = data & ~SMMU_CR0_RESERVED;\n /* in case the command queue has been enabled */\n- smmuv3_cmdq_consume(s, &local_err);\n+ smmuv3_cmdq_consume(s, &err);\n+ /* Allocate vEVENTQ if EVENTQ is enabled and a vIOMMU is available */\n+ smmuv3_accel_alloc_veventq(s, &local_err);\n+ error_propagate(&err, local_err);\n break;\n case A_CR1:\n s->cr[1] = data;\n@@ -1621,7 +1624,7 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,\n * By acknowledging the CMDQ_ERR, SW may notify cmds can\n * be processed again\n */\n- smmuv3_cmdq_consume(s, &local_err);\n+ smmuv3_cmdq_consume(s, &err);\n break;\n case A_GERROR_IRQ_CFG0: /* 64b */\n s->gerror_irq_cfg0 = deposit64(s->gerror_irq_cfg0, 0, 32, data);\n@@ -1643,7 +1646,7 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,\n if (data & R_GBPA_UPDATE_MASK) {\n /* Ignore update bit as write is synchronous. */\n s->gbpa = data & ~R_GBPA_UPDATE_MASK;\n- smmuv3_accel_attach_gbpa_hwpt(s, &local_err);\n+ smmuv3_accel_attach_gbpa_hwpt(s, &err);\n }\n break;\n case A_STRTAB_BASE: /* 64b */\n@@ -1671,7 +1674,7 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,\n break;\n case A_CMDQ_PROD:\n s->cmdq.prod = data;\n- smmuv3_cmdq_consume(s, &local_err);\n+ smmuv3_cmdq_consume(s, &err);\n break;\n case A_CMDQ_CONS:\n s->cmdq.cons = data;\n@@ -1711,8 +1714,8 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,\n break;\n }\n \n- if (local_err) {\n- error_report_err(local_err);\n+ if (err) {\n+ error_report_err(err);\n }\n return MEMTX_OK;\n }\n","prefixes":["v6","3/5"]}