{"id":2196287,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2196287/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260213103942.142823-2-skolothumtho@nvidia.com>","date":"2026-02-13T10:39:38","name":"[v6,1/5] backends/iommufd: Introduce iommufd_backend_alloc_veventq","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"070207ac01fd7338a2dfeafa26bcbd47888ffe12","submitter":{"id":91580,"url":"http://patchwork.ozlabs.org/api/1.0/people/91580/?format=json","name":"Shameer Kolothum","email":"skolothumtho@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260213103942.142823-2-skolothumtho@nvidia.com/mbox/","series":[{"id":492079,"url":"http://patchwork.ozlabs.org/api/1.0/series/492079/?format=json","date":"2026-02-13T10:39:41","name":"vEVENTQ support for accelerated SMMUv3 devices","version":6,"mbox":"http://patchwork.ozlabs.org/series/492079/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2196287/checks/","tags":{},"headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=r3aswSSB;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C","permerror client-ip=2a01:111:f403:c101::7;\n envelope-from=skolothumtho@nvidia.com;\n helo=BL0PR03CU003.outbound.protection.outlook.com"],"From":"Shameer Kolothum <skolothumtho@nvidia.com>","To":"<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>","CC":"<eric.auger@redhat.com>, <peter.maydell@linaro.org>,\n <nicolinc@nvidia.com>, <nathanc@nvidia.com>, <mochs@nvidia.com>,\n <jan@nvidia.com>, <jgg@nvidia.com>, <jonathan.cameron@huawei.com>,\n <zhangfei.gao@linaro.org>, <zhenzhong.duan@intel.com>, <kjaju@nvidia.com>,\n <skolothumtho@nvidia.com>","Subject":"[PATCH v6 1/5] backends/iommufd: Introduce\n iommufd_backend_alloc_veventq","Date":"Fri, 13 Feb 2026 10:39:38 +0000","Message-ID":"<20260213103942.142823-2-skolothumtho@nvidia.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260213103942.142823-1-skolothumtho@nvidia.com>","References":"<20260213103942.142823-1-skolothumtho@nvidia.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-Originating-IP":"[10.126.230.35]","X-ClientProxiedBy":"rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"BL6PEPF0001AB4D:EE_|SA0PR12MB4429:EE_","X-MS-Office365-Filtering-Correlation-Id":"5f2ea19e-b50c-48c1-1ebd-08de6aecac36","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"BCL:0;\n ARA:13230040|376014|36860700013|82310400026|1800799024;","X-Microsoft-Antispam-Message-Info":"\n PWGbDTB6EgZjL/ALqn0TRxsLsa8MW7nwWkavW68HTSgRv3xZR2u8FdeYTnQ05hm+FJG7R2yqSCjrFWGpc1ZolUNQoKOnQbmzFwoPf7owknSW8vwdGrY+zGyfbDkEhmHnP0jX0TPNsGWuXSaisL0rho1OXy2coOgQxd019orrZl7uU0uIWfKRtb/TxzFvwSQ4nZe/tEMlLGwMnne2czl+Fb6zMF7Y0DRhhLdfl/HKcKAmGmDl0lo32sJKCsnh2fvKhGpNcT6msEdtEkD6wV6bnHLKyunvIEkVizUXxUm8QhooOK6IP75RX0pFGUp0wjbsU5VpUhJo+WUvEOXpJR+iv+bJRA33MNgyyHneTR6r4myv1TrdMbsleuKnQyRT9zfbd0DCkspAUl1XdkVJu/I8bzPrQtT2RaVE85kcutNh1/I+L6A6LM6pcaorOBxlorkmiIBCOmMapDCVkbD6JchXNGL+vVPAgfHPQhc5MEUTMFCZnJgyQhyYPH4IrfD+Ck6/AeZmFxGHVN5RCT3ulHaqcHF0wzd4GK4Z8c1RZ0NlUlC5SUYcbm9gJtiUEOUXHZLwAVnfK8mVP+79yPGTlYMgj6p3ioWSDn65jrzv09da1ed/1+dCscixxcXCbZBbDxMME4Z0Uh0QozdcWM4NoNKT8cd7qtMwvgv2AgkfR/FMBKipDWFWTXXVCd3EUqyndVlhGpbz+DSOTzNgOHLyXJ/xeSLEcx+Nh8Od7XKBG9IL39tPM1hKAVyoGKio4XVOX4e17kIBG0Pqodw7PO0f0sZfwQ8O6q7mhrC1DUMxPMyWbyF4skTJrkQnXwSe+sEp5o7E3MwQNfKUk3sMZhnGJAyhP+thhJ2BIIINTlQhw1nMuI6ilQEQSsBOCHQr45N++UZQN09LX5S4+ydLmsr3oreWD7eYHkid6LPK9RaxglB6akQtGfEzuvdb9sxwctBqrVdvNjwzXaJwwyyC9eHY378NFkkLmYM2WpAUcNYBllWaiVZegEOwSpPBUpWjmY6FW5ZmdZMY9ct61zBFZxxIYtZjGLlOQUd2aatHVsavCn7WZ9R8Rq2iVlbZlM2ks22PBTaM3JCkNNRP/1tqnC6RO2lVRPN6odSfAOa6nTPg73emOB0q93IxH2E6/B7ZCfNWvs8fjeGHa98OvbAYHVrnHTqzYL4aaI3uOlOJx9zNoLfCj7RNkyEYjgiya1UIAZxK1im2zEWxpFu3DcbS7kjfPdJVcuKZ8y6ue0kzjRpoyobPEj6P7FaSgrjfAvdIHv3Khx5yOMknCb3Nv0PCyL2iwY/VPAgHWcdhexR+pOogV25heXhhXhQjhwKeNKZjzqDM6ZHrkv+jzrykB0dZjkiZIArKWz6VG7ibGDPrudH9QpUv7lksjsyf1u+vAgejPUbr/WSabTJ3zSH4p7SYbpZb60+AfyB6GZzt5igTzWtLk4w76RKTyziKAXiV/3KeJXrwgCB6WsM6niX61lFx5Tq1lll8ue2P5JkAO3gsI7QS0OsyZPXBKGI3CxQQlIU8Y+AreDrl7QFeRjmzVmulsh8P81PF8NiE8Vz6cJTL52mkjEI7EGDk6I6G5XA/dJ50J7G7Nl4cs4Cn7079rtjXs8JJdlaJp8Z0TvyqL8LnYArh1XiXf3UvC8LyhnxMH+HJnliMb/mv/Xn7CwWqwrkI5NmqMg2sAg==","X-Forefront-Antispam-Report":"CIP:216.228.117.161; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n BL6PEPF0001AB4D.namprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"SA0PR12MB4429","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_NONE=0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development <qemu-devel.nongnu.org>","List-Unsubscribe":"<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<https://lists.nongnu.org/archive/html/qemu-devel>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Nicolin Chen <nicolinc@nvidia.com>\n\nAdd a new helper for IOMMU_VEVENTQ_ALLOC ioctl to allocate a virtual event\nqueue (vEVENTQ) for a vIOMMU object.\n\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\nTested-by: Nicolin Chen <nicolinc@nvidia.com>\nReviewed-by: Eric Auger <eric.auger@redhat.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n backends/iommufd.c       | 31 +++++++++++++++++++++++++++++++\n backends/trace-events    |  1 +\n include/system/iommufd.h | 12 ++++++++++++\n 3 files changed, 44 insertions(+)","diff":"diff --git a/backends/iommufd.c b/backends/iommufd.c\nindex 13822df82f..acfab907c0 100644\n--- a/backends/iommufd.c\n+++ b/backends/iommufd.c\n@@ -504,6 +504,37 @@ bool iommufd_backend_alloc_vdev(IOMMUFDBackend *be, uint32_t dev_id,\n     return true;\n }\n \n+bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be, uint32_t viommu_id,\n+                                   uint32_t type, uint32_t depth,\n+                                   uint32_t *out_veventq_id,\n+                                   uint32_t *out_veventq_fd, Error **errp)\n+{\n+    int ret;\n+    struct iommu_veventq_alloc alloc_veventq = {\n+        .size = sizeof(alloc_veventq),\n+        .flags = 0,\n+        .type = type,\n+        .veventq_depth = depth,\n+        .viommu_id = viommu_id,\n+    };\n+\n+    ret = ioctl(be->fd, IOMMU_VEVENTQ_ALLOC, &alloc_veventq);\n+\n+    trace_iommufd_viommu_alloc_eventq(be->fd, viommu_id, type,\n+                                      alloc_veventq.out_veventq_id,\n+                                      alloc_veventq.out_veventq_fd, ret);\n+    if (ret) {\n+        error_setg_errno(errp, errno, \"IOMMU_VEVENTQ_ALLOC failed\");\n+        return false;\n+    }\n+\n+    g_assert(out_veventq_id);\n+    g_assert(out_veventq_fd);\n+    *out_veventq_id = alloc_veventq.out_veventq_id;\n+    *out_veventq_fd = alloc_veventq.out_veventq_fd;\n+    return true;\n+}\n+\n bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev,\n                                            uint32_t hwpt_id, Error **errp)\n {\ndiff --git a/backends/trace-events b/backends/trace-events\nindex 8dc64a20d3..b9365113e7 100644\n--- a/backends/trace-events\n+++ b/backends/trace-events\n@@ -23,6 +23,7 @@ iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t iova, u\n iommufd_backend_invalidate_cache(int iommufd, uint32_t id, uint32_t data_type, uint32_t entry_len, uint32_t entry_num, uint32_t done_num, uint64_t data_ptr, int ret) \" iommufd=%d id=%u data_type=%u entry_len=%u entry_num=%u done_num=%u data_ptr=0x%\"PRIx64\" (%d)\"\n iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, uint32_t hwpt_id, uint32_t viommu_id, int ret) \" iommufd=%d type=%u dev_id=%u hwpt_id=%u viommu_id=%u (%d)\"\n iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_id, uint64_t virt_id, uint32_t vdev_id, int ret) \" iommufd=%d dev_id=%u viommu_id=%u virt_id=0x%\"PRIx64\" vdev_id=%u (%d)\"\n+iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type, uint32_t veventq_id, uint32_t veventq_fd, int ret) \" iommufd=%d viommu_id=%u type=%u veventq_id=%u veventq_fd=%u (%d)\"\n \n # igvm-cfg.c\n igvm_reset_enter(int type) \"type=%u\"\ndiff --git a/include/system/iommufd.h b/include/system/iommufd.h\nindex 80d72469a9..e4ca16da70 100644\n--- a/include/system/iommufd.h\n+++ b/include/system/iommufd.h\n@@ -56,6 +56,13 @@ typedef struct IOMMUFDVdev {\n     uint32_t virt_id;  /* virtual device ID */\n } IOMMUFDVdev;\n \n+/* Virtual event queue interface for a vIOMMU */\n+typedef struct IOMMUFDVeventq {\n+    IOMMUFDViommu *viommu;\n+    uint32_t veventq_id;\n+    uint32_t veventq_fd;\n+} IOMMUFDVeventq;\n+\n bool iommufd_backend_connect(IOMMUFDBackend *be, Error **errp);\n void iommufd_backend_disconnect(IOMMUFDBackend *be);\n \n@@ -86,6 +93,11 @@ bool iommufd_backend_alloc_vdev(IOMMUFDBackend *be, uint32_t dev_id,\n                                 uint32_t viommu_id, uint64_t virt_id,\n                                 uint32_t *out_vdev_id, Error **errp);\n \n+bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be, uint32_t viommu_id,\n+                                   uint32_t type, uint32_t depth,\n+                                   uint32_t *out_veventq_id,\n+                                   uint32_t *out_veventq_fd, Error **errp);\n+\n bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_id,\n                                         bool start, Error **errp);\n bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id,\n","prefixes":["v6","1/5"]}