{"id":2196237,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2196237/?format=json","project":{"id":57,"url":"http://patchwork.ozlabs.org/api/1.0/projects/57/?format=json","name":"Linux ASPEED SoC development","link_name":"linux-aspeed","list_id":"linux-aspeed.lists.ozlabs.org","list_email":"linux-aspeed@lists.ozlabs.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260213-pinctrl-single-bit-v1-1-c60f2fb80efb@aspeedtech.com>","date":"2026-02-13T08:17:42","name":"[RFC,1/2] dt-bindings: pinctrl: Add pinctrl-packed","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"350587a2052b6a7d0f6292d4293a9a2dde10716c","submitter":{"id":80235,"url":"http://patchwork.ozlabs.org/api/1.0/people/80235/?format=json","name":"Billy Tsai","email":"billy_tsai@aspeedtech.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-aspeed/patch/20260213-pinctrl-single-bit-v1-1-c60f2fb80efb@aspeedtech.com/mbox/","series":[{"id":492066,"url":"http://patchwork.ozlabs.org/api/1.0/series/492066/?format=json","date":"2026-02-13T08:17:43","name":"pinctrl: add syscon-backed packed-field pinctrl driver and DT bindings","version":1,"mbox":"http://patchwork.ozlabs.org/series/492066/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2196237/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-aspeed@lists.ozlabs.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; 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lists.ozlabs.org;\n dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com;\n spf=pass (client-ip=211.20.114.72; helo=twmbx01.aspeed.com;\n envelope-from=billy_tsai@aspeedtech.com;\n receiver=lists.ozlabs.org) smtp.mailfrom=aspeedtech.com","From":"Billy Tsai ","Date":"Fri, 13 Feb 2026 16:17:42 +0800","Subject":"[PATCH RFC 1/2] dt-bindings: pinctrl: Add pinctrl-packed","X-Mailing-List":"linux-aspeed@lists.ozlabs.org","List-Id":"","List-Help":"","List-Owner":"","List-Post":"","List-Archive":",\n ","List-Subscribe":",\n ,\n ","List-Unsubscribe":"","Precedence":"list","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-ID":"<20260213-pinctrl-single-bit-v1-1-c60f2fb80efb@aspeedtech.com>","References":"<20260213-pinctrl-single-bit-v1-0-c60f2fb80efb@aspeedtech.com>","In-Reply-To":"<20260213-pinctrl-single-bit-v1-0-c60f2fb80efb@aspeedtech.com>","To":"Linus Walleij , Tony Lindgren , \"Rob\n Herring\" , Krzysztof Kozlowski , \"Conor\n Dooley\" , Joel Stanley , Andrew Jeffery\n\t, Bartosz Golaszewski ","CC":", ,\n\t, ,\n\t, ,\n\t, Billy Tsai ","X-Mailer":"b4 0.14.3","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1770970675; l=6251;\n i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id;\n bh=btGp9Y9DY2YDzIKxQ4nzYfeU8KTNhNWyQaI1KcxpA8s=;\n b=s7ZgCtBuEJiKRU4PE4pTcsjmidOPe6Pr3I1F2LQbrMy2qT2AWW6Qip1McM+yHx0XX+Y2n7bVc\n zLiNwujNN/bAUthtPElUQpJiisIpUfI06GadbLUWPhHZhIFmTf8Wot1","X-Developer-Key":"i=billy_tsai@aspeedtech.com; a=ed25519;\n pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ=","X-Spam-Status":"No, score=0.0 required=5.0 tests=SPF_HELO_FAIL,SPF_PASS\n\tautolearn=disabled version=4.0.1","X-Spam-Checker-Version":"SpamAssassin 4.0.1 (2024-03-25) on lists.ozlabs.org"},"content":"Add a Devicetree binding for a generic pin controller where pinmux and/or\npin configuration are represented as fixed-width fields packed\nsequentially within shared registers.\n\nThe binding targets controllers that are typically exposed as subnodes of\na syscon node and accessed via regmap-mmio through the parent.\n\nSigned-off-by: Billy Tsai \n---\n .../bindings/pinctrl/pinctrl-packed.yaml | 166 +++++++++++++++++++++\n 1 file changed, 166 insertions(+)","diff":"diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-packed.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-packed.yaml\nnew file mode 100644\nindex 000000000000..dd01ba2fed71\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-packed.yaml\n@@ -0,0 +1,166 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/pinctrl-packed.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Generic Pin Controller with Packed-Field Registers\n+\n+maintainers:\n+ - Billy Tsai \n+\n+description:\n+ This binding describes pin controller hardware where pinmux and/or\n+ pin configuration fields are represented as fixed-width fields packed\n+ sequentially within shared registers.\n+\n+ Such controllers are commonly embedded within a larger system control\n+ unit (SCU) register block and may be exposed as subnodes of a syscon\n+ device.\n+\n+ Conceptually, this model is related to the pinctrl-single binding,\n+ but instead of describing individual register offsets via\n+ tuples, the hardware provides fixed-width,\n+ per-pin fields packed linearly within shared registers.\n+\n+properties:\n+ compatible:\n+ oneOf:\n+ - enum:\n+ - pinctrl-packed\n+ - pinconf-packed\n+\n+ reg:\n+ maxItems: 1\n+\n+ '#pinctrl-cells':\n+ description:\n+ The pinctrl provider uses standard state nodes referenced by pinctrl-N\n+ properties; consumers do not pass per-pin arguments via phandle.\n+ const: 1\n+\n+ pinctrl-packed,function-mask:\n+ description: Mask of the allowed register bits for a single pin.\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+\n+ pinctrl-packed,gpio-range:\n+ description: Optional list of pin base, nr pins & gpio function.\n+ $ref: /schemas/types.yaml#/definitions/phandle-array\n+ items:\n+ items:\n+ - description: phandle of a gpio-range node\n+ - description: pin base\n+ - description: number of pins\n+ - description: gpio function\n+\n+patternProperties:\n+ '-pins(-[0-9]+)?$|-pin$':\n+ type: object\n+ additionalProperties: false\n+\n+ properties:\n+ pinctrl-packed,pins:\n+ description: Array of pin index and function selector pairs.\n+ $ref: /schemas/types.yaml#/definitions/uint32-array\n+\n+ pinctrl-packed,bias-pullup:\n+ description: Optional bias pull-up configuration.\n+ $ref: /schemas/types.yaml#/definitions/uint32-array\n+ maxItems: 4\n+ items:\n+ - description: Input value.\n+ - description: Enabled pull-up bits.\n+ - description: Disabled pull-up bits.\n+ - description: Pull-up mask.\n+ additionalItems: false\n+\n+ pinctrl-packed,bias-pulldown:\n+ description: Optional bias pull-down configuration.\n+ $ref: /schemas/types.yaml#/definitions/uint32-array\n+ maxItems: 4\n+ items:\n+ - description: Input value.\n+ - description: Enabled pull-down bits.\n+ - description: Disabled pull-down bits.\n+ - description: Pull-down mask.\n+ additionalItems: false\n+\n+ pinctrl-packed,drive-strength:\n+ description: Optional drive strength configuration.\n+ $ref: /schemas/types.yaml#/definitions/uint32-array\n+ maxItems: 2\n+ items:\n+ - description: Drive strength value.\n+ - description: Drive strength mask.\n+ additionalItems: false\n+\n+ pinctrl-packed,input-schmitt:\n+ description: Optional input Schmitt trigger configuration.\n+ $ref: /schemas/types.yaml#/definitions/uint32-array\n+ maxItems: 2\n+ items:\n+ - description: Schmitt trigger value.\n+ - description: Schmitt trigger mask.\n+ additionalItems: false\n+\n+ pinctrl-packed,input-schmitt-enable:\n+ description: Optional input Schmitt enable configuration.\n+ $ref: /schemas/types.yaml#/definitions/uint32-array\n+ maxItems: 4\n+ items:\n+ - description: Input value.\n+ - description: Enable bits.\n+ - description: Disable bits.\n+ - description: Schmitt mask.\n+ additionalItems: false\n+\n+ pinctrl-packed,low-power-mode:\n+ description: Optional low power mode configuration.\n+ $ref: /schemas/types.yaml#/definitions/uint32-array\n+ maxItems: 2\n+ items:\n+ - description: Low power value.\n+ - description: Low power mask.\n+ additionalItems: false\n+\n+ pinctrl-packed,slew-rate:\n+ description: Optional slew rate configuration.\n+ $ref: /schemas/types.yaml#/definitions/uint32-array\n+ maxItems: 2\n+ items:\n+ - description: Slew rate value.\n+ - description: Slew rate mask.\n+ additionalItems: false\n+\n+required:\n+ - compatible\n+ - reg\n+ - \"#pinctrl-cells\"\n+ - pinctrl-packed,function-mask\n+\n+additionalProperties: false\n+\n+allOf:\n+ - $ref: pinctrl.yaml#\n+\n+examples:\n+ - |\n+ syscon@0 {\n+ compatible = \"syscon\", \"simple-mfd\";\n+ reg = <0x0 0x1000>;\n+ ranges;\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+\n+ pinctrl@400 {\n+ compatible = \"pinctrl-packed\";\n+ reg = <0x400 0x80>;\n+ #pinctrl-cells = <1>;\n+ pinctrl-packed,function-mask = <0xf>;\n+\n+ uart0-pins {\n+ /* pairs */\n+ pinctrl-packed,pins = <0 2>, <1 2>;\n+ };\n+ };\n+ };\n","prefixes":["RFC","1/2"]}