{"id":2175856,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175856/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20251219-aspeed-sgpio-v5-2-fd5593178144@google.com>","date":"2025-12-19T07:04:15","name":"[v5,2/6] hw/gpio/aspeed_sgpio: Add QOM property accessors for SGPIO pins","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"4c109d48e69407694ffe1ed2dd797acb262e178c","submitter":{"id":91652,"url":"http://patchwork.ozlabs.org/api/1.0/people/91652/?format=json","name":"Yubin Zou","email":"yubinz@google.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20251219-aspeed-sgpio-v5-2-fd5593178144@google.com/mbox/","series":[{"id":485958,"url":"http://patchwork.ozlabs.org/api/1.0/series/485958/?format=json","date":"2025-12-19T07:04:13","name":"hw/gpio/aspeed_sgpio: Add Aspeed Serial GPIO (SGPIO) controller model","version":5,"mbox":"http://patchwork.ozlabs.org/series/485958/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175856/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256\n header.s=20230601 header.b=PwqX2xjm;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dXdqT0dhRz1xty\n\tfor ; Fri, 19 Dec 2025 18:06:13 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1vWUXf-0003qo-90; Fri, 19 Dec 2025 02:04:47 -0500","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from\n <3CflEaQYKCmAWS9GLXEMMEJC.AMKOCKS-BCTCJLMLELS.MPE@flex--yubinz.bounces.google.com>)\n id 1vWUXd-0003oZ-Il\n for qemu-devel@nongnu.org; Fri, 19 Dec 2025 02:04:45 -0500","from mail-pj1-x104a.google.com ([2607:f8b0:4864:20::104a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from\n <3CflEaQYKCmAWS9GLXEMMEJC.AMKOCKS-BCTCJLMLELS.MPE@flex--yubinz.bounces.google.com>)\n id 1vWUXb-0001Yy-QD\n for qemu-devel@nongnu.org; Fri, 19 Dec 2025 02:04:45 -0500","by mail-pj1-x104a.google.com with SMTP id\n 98e67ed59e1d1-34e70e2e363so3018842a91.1\n for ; Thu, 18 Dec 2025 23:04:42 -0800 (PST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=google.com; s=20230601; t=1766127882; x=1766732682; darn=nongnu.org;\n h=cc:to:from:subject:message-id:references:mime-version:in-reply-to\n :date:from:to:cc:subject:date:message-id:reply-to;\n bh=/qqf5+bwzclxk1ILtr6MR3xBusLE6u4kKKSubpiajjE=;\n b=PwqX2xjmnQeHFq5Ezapkyh4GCgd4zB9rS2UDeFP4Osg00BossDuRUrLetyfYNfwkEB\n HpiXKxPCqdRPlWM1Skm2+UKKowxnGJuja7KyRXhlSj1aIG5BWmmJKwWbDWztuVetkr32\n OHwlGotlqBs5dmIo6U3qJhesAlpeKTxF/bBa1mvD1gS25YO4PK85GuUU5ddK3bJ9OdkN\n c972EvOD7hzNYGrR8EUlDIjaiwjz2XgjblGO1VtL4qO4riR3nc97/p5dpYWpqeca7ose\n wMozJMR0xkM3UWqy0j/3FnRoDkX6FAHnQx92rcFIMXsLKn7QUC5ExtWlxAszDx/jPlOl\n BCjw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1766127882; x=1766732682;\n h=cc:to:from:subject:message-id:references:mime-version:in-reply-to\n :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to;\n bh=/qqf5+bwzclxk1ILtr6MR3xBusLE6u4kKKSubpiajjE=;\n b=qlin0qHiaJ4UZidLge8DRPcInny4LuPqY3vd1eL1gpKhhuzTqtoiDIGs+uAP///m9Q\n mDetlp37v0P3UZAjgGf/FSIk5nEfS/jTFe4Xo7KPMjkOWwTSOoM6siIVyaoqaaIhX/zj\n dYaSQUvpdX2i/qfLM2Lwd+jlsxV1Yy7KAV6ALFV+FciaTAVTenKp/Qfk/9btGZNSuEL8\n s0F8plqzRdVrn7CFCnjcqGbjPehuD7dLGEH/0WLbfwmMPKImtlCIkE6hfjTukrFBlYGw\n 5OeMPeHb+asKbY/nmhXDjHwD3AMZQ66/3k1wsCjFXYVF62ef9KS2nOEEXFB8dt1/qNKB\n XFvQ==","X-Gm-Message-State":"AOJu0Yy+5io/bK860r0LADVvdfv4llq/T5uY5OW37EjqTyUWALXbEaqo\n ty3Ms9kXzqbIe6YXO1UNN0RnAH9vTVUIhqycB685RtBLowmEjvlfp1YUJrY884fCAHME2xcmq/o\n G5HUgfLuaRAx2jIei8D86kDNAYYSgUqMhhTZ7xyAVE4xTJQCGJVikvk7rw8fdvcMb1K+XYruFBb\n K6fLXNip8HacqrvOIMdZrMTqdCKCehkS8OKco=","X-Google-Smtp-Source":"\n AGHT+IHWHAgGN4JmRn3r9yaFEWteE3bUnOyeMcedfZozH1aAn6LnBb4zNlAafZIs5GpHIMnZ9eaz/9KFyJc=","X-Received":"from dlah7.prod.google.com ([2002:a05:701b:2607:b0:11d:cd2a:4c1b])\n (user=yubinz job=prod-delivery.src-stubby-dispatcher) by\n 2002:a05:7022:4287:b0:11b:9386:a3c8\n with SMTP id a92af1059eb24-121723018d9mr2541572c88.41.1766127881370; Thu, 18\n Dec 2025 23:04:41 -0800 (PST)","Date":"Fri, 19 Dec 2025 07:04:15 +0000","In-Reply-To":"<20251219-aspeed-sgpio-v5-0-fd5593178144@google.com>","Mime-Version":"1.0","References":"<20251219-aspeed-sgpio-v5-0-fd5593178144@google.com>","X-Mailer":"b4 0.14.2","Message-ID":"<20251219-aspeed-sgpio-v5-2-fd5593178144@google.com>","Subject":"[PATCH v5 2/6] hw/gpio/aspeed_sgpio: Add QOM property accessors for\n SGPIO pins","From":"Yubin Zou ","To":"qemu-devel@nongnu.org","Cc":"\" =?utf-8?q?C=C3=A9dric_Le_Goater?= \" ,\n Peter Maydell ,\n Steven Lee , Troy Lee ,\n Jamin Lin ,\n Andrew Jeffery , Joel Stanley ,\n Fabiano Rosas , Laurent Vivier ,\n Paolo Bonzini ,\n Kane-Chen-AS ,\n Nabih Estefan , qemu-arm@nongnu.org,\n Yubin Zou ","Content-Type":"text/plain; charset=\"utf-8\"","Received-SPF":"pass client-ip=2607:f8b0:4864:20::104a;\n envelope-from=3CflEaQYKCmAWS9GLXEMMEJC.AMKOCKS-BCTCJLMLELS.MPE@flex--yubinz.bounces.google.com;\n helo=mail-pj1-x104a.google.com","X-Spam_score_int":"-95","X-Spam_score":"-9.6","X-Spam_bar":"---------","X-Spam_report":"(-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"The `aspeed_sgpio_get_pin` and `aspeed_sgpio_set_pin` functions are\nimplemented to get and set the level of individual SGPIO pins. These\nare then exposed as boolean properties on the SGPIO device object.\n\nSigned-off-by: Yubin Zou \nReviewed-by: Kane Chen \n---\n hw/gpio/aspeed_sgpio.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 79 insertions(+)","diff":"diff --git a/hw/gpio/aspeed_sgpio.c b/hw/gpio/aspeed_sgpio.c\nindex 167a72c41e96c67bd1867a19e2b1706f5bd074e4..927c711cb3aef889c47c9a9156fe4241981c5efa 100644\n--- a/hw/gpio/aspeed_sgpio.c\n+++ b/hw/gpio/aspeed_sgpio.c\n@@ -51,6 +51,8 @@ static uint64_t aspeed_sgpio_2700_read(void *opaque, hwaddr offset,\n reg = offset >> 2;\n \n switch (reg) {\n+ case R_SGPIO_INT_STATUS_0 ... R_SGPIO_INT_STATUS_7:\n+ break;\n case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL:\n value = aspeed_sgpio_2700_read_control_reg(s, reg);\n break;\n@@ -82,6 +84,73 @@ static void aspeed_sgpio_2700_write(void *opaque, hwaddr offset, uint64_t data,\n }\n }\n \n+static bool aspeed_sgpio_get_pin_level(AspeedSGPIOState *s, int pin)\n+{\n+ uint32_t value = s->ctrl_regs[pin >> 1];\n+ bool is_input = !(pin % 2);\n+ uint32_t bit_mask = 0;\n+\n+ if (is_input) {\n+ bit_mask = SGPIO_SERIAL_IN_VAL_MASK;\n+ } else {\n+ bit_mask = SGPIO_SERIAL_OUT_VAL_MASK;\n+ }\n+\n+ return value & bit_mask;\n+}\n+\n+static void aspeed_sgpio_set_pin_level(AspeedSGPIOState *s, int pin, bool level)\n+{\n+ uint32_t value = s->ctrl_regs[pin >> 1];\n+ bool is_input = !(pin % 2);\n+ uint32_t bit_mask = 0;\n+\n+ if (is_input) {\n+ bit_mask = SGPIO_SERIAL_IN_VAL_MASK;\n+ } else {\n+ bit_mask = SGPIO_SERIAL_OUT_VAL_MASK;\n+ }\n+\n+ if (level) {\n+ value |= bit_mask;\n+ } else {\n+ value &= ~bit_mask;\n+ }\n+ s->ctrl_regs[pin >> 1] = value;\n+}\n+\n+static void aspeed_sgpio_get_pin(Object *obj, Visitor *v, const char *name,\n+ void *opaque, Error **errp)\n+{\n+ bool level = true;\n+ int pin = 0xfff;\n+ AspeedSGPIOState *s = ASPEED_SGPIO(obj);\n+\n+ if (sscanf(name, \"sgpio%03d\", &pin) != 1) {\n+ error_setg(errp, \"%s: error reading %s\", __func__, name);\n+ return;\n+ }\n+ level = aspeed_sgpio_get_pin_level(s, pin);\n+ visit_type_bool(v, name, &level, errp);\n+}\n+\n+static void aspeed_sgpio_set_pin(Object *obj, Visitor *v, const char *name,\n+ void *opaque, Error **errp)\n+{\n+ bool level;\n+ int pin = 0xfff;\n+ AspeedSGPIOState *s = ASPEED_SGPIO(obj);\n+\n+ if (!visit_type_bool(v, name, &level, errp)) {\n+ return;\n+ }\n+ if (sscanf(name, \"sgpio%03d\", &pin) != 1) {\n+ error_setg(errp, \"%s: error reading %s\", __func__, name);\n+ return;\n+ }\n+ aspeed_sgpio_set_pin_level(s, pin, level);\n+}\n+\n static const MemoryRegionOps aspeed_sgpio_2700_ops = {\n .read = aspeed_sgpio_2700_read,\n .write = aspeed_sgpio_2700_write,\n@@ -105,6 +174,15 @@ static void aspeed_sgpio_realize(DeviceState *dev, Error **errp)\n sysbus_init_mmio(sbd, &s->iomem);\n }\n \n+static void aspeed_sgpio_init(Object *obj)\n+{\n+ for (int i = 0; i < ASPEED_SGPIO_MAX_PIN_PAIR * 2; i++) {\n+ g_autofree char *name = g_strdup_printf(\"sgpio%03d\", i);\n+ object_property_add(obj, name, \"bool\", aspeed_sgpio_get_pin,\n+ aspeed_sgpio_set_pin, NULL, NULL);\n+ }\n+}\n+\n static void aspeed_sgpio_class_init(ObjectClass *klass, const void *data)\n {\n DeviceClass *dc = DEVICE_CLASS(klass);\n@@ -134,6 +212,7 @@ static const TypeInfo aspeed_sgpio_ast2700_info = {\n .name = TYPE_ASPEED_SGPIO \"-ast2700\",\n .parent = TYPE_ASPEED_SGPIO,\n .class_init = aspeed_sgpio_2700_class_init,\n+ .instance_init = aspeed_sgpio_init,\n };\n \n static void aspeed_sgpio_register_types(void)\n","prefixes":["v5","2/6"]}