{"id":2175854,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175854/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20251219-aspeed-sgpio-v5-5-fd5593178144@google.com>","date":"2025-12-19T07:04:18","name":"[v5,5/6] hw/arm/aspeed_ast27x0: Wire SGPIO controller to AST2700 SoC","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6a48db8020a5592d9496659b92dd157378b4684e","submitter":{"id":91652,"url":"http://patchwork.ozlabs.org/api/1.0/people/91652/?format=json","name":"Yubin Zou","email":"yubinz@google.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20251219-aspeed-sgpio-v5-5-fd5593178144@google.com/mbox/","series":[{"id":485958,"url":"http://patchwork.ozlabs.org/api/1.0/series/485958/?format=json","date":"2025-12-19T07:04:13","name":"hw/gpio/aspeed_sgpio: Add Aspeed Serial GPIO (SGPIO) controller model","version":5,"mbox":"http://patchwork.ozlabs.org/series/485958/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175854/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256\n header.s=20230601 header.b=gkFJOIBc;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 18\n Dec 2025 23:04:46 -0800 (PST)","Date":"Fri, 19 Dec 2025 07:04:18 +0000","In-Reply-To":"<20251219-aspeed-sgpio-v5-0-fd5593178144@google.com>","Mime-Version":"1.0","References":"<20251219-aspeed-sgpio-v5-0-fd5593178144@google.com>","X-Mailer":"b4 0.14.2","Message-ID":"<20251219-aspeed-sgpio-v5-5-fd5593178144@google.com>","Subject":"[PATCH v5 5/6] hw/arm/aspeed_ast27x0: Wire SGPIO controller to\n AST2700 SoC","From":"Yubin Zou ","To":"qemu-devel@nongnu.org","Cc":"\" =?utf-8?q?C=C3=A9dric_Le_Goater?= \" ,\n Peter Maydell ,\n Steven Lee , Troy Lee ,\n Jamin Lin ,\n Andrew Jeffery , Joel Stanley ,\n Fabiano Rosas , Laurent Vivier ,\n Paolo Bonzini ,\n Kane-Chen-AS ,\n Nabih Estefan , qemu-arm@nongnu.org,\n Yubin Zou ,\n \" =?utf-8?q?C=C3=A9dric_Le_Goater?= \" ","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2607:f8b0:4864:20::649;\n envelope-from=3DvlEaQYKCmUbXELQcJRRJOH.FRPTHPX-GHYHOQRQJQX.RUJ@flex--yubinz.bounces.google.com;\n helo=mail-pl1-x649.google.com","X-Spam_score_int":"-95","X-Spam_score":"-9.6","X-Spam_bar":"---------","X-Spam_report":"(-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This commit integrates the Aspeed SGPIO controller into the AST2700\n\nSigned-off-by: Yubin Zou \nReviewed-by: Cédric Le Goater \n---\n hw/arm/aspeed_ast27x0.c | 16 ++++++++++++++++\n 1 file changed, 16 insertions(+)","diff":"diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c\nindex e5f04bd16e80696e41005d9062a6df6d060b8088..787accadbecae376d0c747d054ec6372785375b1 100644\n--- a/hw/arm/aspeed_ast27x0.c\n+++ b/hw/arm/aspeed_ast27x0.c\n@@ -519,6 +519,11 @@ static void aspeed_soc_ast2700_init(Object *obj)\n snprintf(typename, sizeof(typename), \"aspeed.gpio-%s\", socname);\n object_initialize_child(obj, \"gpio\", &s->gpio, typename);\n \n+ snprintf(typename, sizeof(typename), \"aspeed.sgpio-%s\", socname);\n+ for (i = 0; i < sc->sgpio_num; i++) {\n+ object_initialize_child(obj, \"sgpio[*]\", &s->sgpiom[i], typename);\n+ }\n+\n object_initialize_child(obj, \"rtc\", &s->rtc, TYPE_ASPEED_RTC);\n \n snprintf(typename, sizeof(typename), \"aspeed.sdhci-%s\", socname);\n@@ -973,6 +978,17 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)\n sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,\n aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_GPIO));\n \n+ /* SGPIO */\n+ for (i = 0; i < sc->sgpio_num; i++) {\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sgpiom[i]), errp)) {\n+ return;\n+ }\n+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sgpiom[i]), 0,\n+ sc->memmap[ASPEED_DEV_SGPIOM0 + i]);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->sgpiom[i]), 0,\n+ aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_SGPIOM0 + i));\n+ }\n+\n /* RTC */\n if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {\n return;\n","prefixes":["v5","5/6"]}