{"id":2175813,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175813/?format=json","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.0/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20251218-clk-mtk-mt8365-fixes-v1-7-4f8ff0de3268@baylibre.com>","date":"2025-12-18T23:23:27","name":"[7/9] clk: mediatek: allow gates in topckgen drivers","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"2df5866425492e62fb1848bc832c8d9622493bea","submitter":{"id":87228,"url":"http://patchwork.ozlabs.org/api/1.0/people/87228/?format=json","name":"David Lechner","email":"dlechner@baylibre.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/1.0/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20251218-clk-mtk-mt8365-fixes-v1-7-4f8ff0de3268@baylibre.com/mbox/","series":[{"id":485931,"url":"http://patchwork.ozlabs.org/api/1.0/series/485931/?format=json","date":"2025-12-18T23:23:20","name":"clk: mediatek: mt8365: fix clocks","version":1,"mbox":"http://patchwork.ozlabs.org/series/485931/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175813/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=HhxqxYC6;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20251218-clk-mtk-mt8365-fixes-v1-7-4f8ff0de3268@baylibre.com>","References":"<20251218-clk-mtk-mt8365-fixes-v1-0-4f8ff0de3268@baylibre.com>","In-Reply-To":"<20251218-clk-mtk-mt8365-fixes-v1-0-4f8ff0de3268@baylibre.com>","To":"Julien Masson , Tom Rini ,\n Lukasz Majewski , Ryder Lee ,\n Weijie Gao ,\n Chunfeng Yun ,\n Igor Belwon ,\n GSS_MTK_Uboot_upstream ","Cc":"Julien Stephan , u-boot@lists.denx.de,\n David Lechner ","X-Mailer":"b4 0.14.3","X-Developer-Signature":"v=1; a=openpgp-sha256; l=4310; i=dlechner@baylibre.com;\n h=from:subject:message-id;\n bh=VTQb0wPygvFq7lX9ZsvswsYreIjNQQ8htn6irAWc6W8=;\n b=owEBhAF7/pANAwAKAcLMIAH/AY/AAcsmYgBpRI0cHLUQv2PL/m0/1SE+eqn9uPSi/nNIV4vHt\n O7w4ha2AreJAUoEAAEKADQWIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUSNHBYcZGxlY2huZXJA\n YmF5bGlicmUuY29tAAoJEMLMIAH/AY/A2nsH/jE6SysRU8PxFSIe1j1XCk1KIfnQszNlw0nQgDe\n uSvnuPaJtK7qIy6iESq38OMrOw/CHEn/mGL27HKOVrQrYbgaz0UGBBTFDHLznaLCBYJD5Vyspmh\n /ZRdTdCJmjNiY3OY8ULFGS/xXunXi0fVvd13evdq75tN30QrQ9S9p40Py1iLT6POPf6Ly+6e8NQ\n 3JsyLfJ0idhJvhfSRqqE6eJrYFok+i95ILEZaT3rgVxfrbxftTVxCdZvRmUr1OS1gwuBdf9z/Kd\n aJ1ciZ86b3BVkMwnHP9K11jKeGDbxyb47lTZwObT72ILXVf8ArpEUPMTwtr2geNhieUFD5SCHD3\n oAlQ=","X-Developer-Key":"i=dlechner@baylibre.com; a=openpgp;\n fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03","X-Mailman-Approved-At":"Fri, 19 Dec 2025 00:28:35 +0100","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Add handling for gates in the topckgen clk drivers. This avoids the need\nto have separate topckgen-cg drivers and devicetree nodes for the same\naddress space and clock ID range.\n\nSigned-off-by: David Lechner \n---\n drivers/clk/mediatek/clk-mtk.c | 61 +++++++++++++++++++++++++++++++++++++++---\n 1 file changed, 57 insertions(+), 4 deletions(-)","diff":"diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c\nindex e370d304c03..82306ae285c 100644\n--- a/drivers/clk/mediatek/clk-mtk.c\n+++ b/drivers/clk/mediatek/clk-mtk.c\n@@ -582,7 +582,7 @@ static const int mtk_topckgen_of_xlate(struct clk *clk,\n \tif (ret)\n \t\treturn ret;\n \n-\t/* topckgen only uses fclks, fdivs and muxes. */\n+\t/* topckgen only uses fclks, fdivs, muxes and gates. */\n \n \tif (tree->fclks && clk->id < tree->num_fclks)\n \t\treturn 0;\n@@ -595,6 +595,10 @@ static const int mtk_topckgen_of_xlate(struct clk *clk,\n \t clk->id < tree->muxes_offs + tree->num_muxes)\n \t\treturn 0;\n \n+\tif (tree->gates && clk->id >= tree->gates_offs &&\n+\t clk->id < tree->gates_offs + tree->num_gates)\n+\t\treturn 0;\n+\n \treturn -ENOENT;\n }\n \n@@ -696,6 +700,14 @@ static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk,\n static ulong mtk_topckgen_get_rate(struct clk *clk)\n {\n \tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n+\tconst struct mtk_clk_tree *tree = priv->tree;\n+\n+\tif (tree->gates && clk->id >= tree->gates_offs &&\n+\t clk->id < tree->gates_offs + tree->num_gates) {\n+\t\tconst struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs];\n+\n+\t\treturn mtk_clk_find_parent_rate(clk, gate->parent, NULL);\n+\t}\n \n \tif (clk->id < priv->tree->fdivs_offs)\n \t\treturn priv->tree->fclks[clk->id].rate;\n@@ -740,6 +752,21 @@ static int mtk_clk_mux_enable(struct clk *clk)\n \treturn 0;\n }\n \n+static int mtk_topckgen_enable(struct clk *clk)\n+{\n+\tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n+\tconst struct mtk_clk_tree *tree = priv->tree;\n+\n+\tif (tree->gates && clk->id >= tree->gates_offs &&\n+\t clk->id < tree->gates_offs + tree->num_gates) {\n+\t\tconst struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs];\n+\n+\t\treturn mtk_gate_enable(priv->base, gate);\n+\t}\n+\n+\treturn mtk_clk_mux_enable(clk);\n+}\n+\n static int mtk_clk_mux_disable(struct clk *clk)\n {\n \tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n@@ -766,13 +793,29 @@ static int mtk_clk_mux_disable(struct clk *clk)\n \treturn 0;\n }\n \n+static int mtk_topckgen_disable(struct clk *clk)\n+{\n+\tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n+\tconst struct mtk_clk_tree *tree = priv->tree;\n+\n+\tif (tree->gates && clk->id >= tree->gates_offs &&\n+\t clk->id < tree->gates_offs + tree->num_gates) {\n+\t\tconst struct mtk_gate *gate = &tree->gates[clk->id - tree->gates_offs];\n+\n+\t\treturn mtk_gate_disable(priv->base, gate);\n+\t}\n+\n+\treturn mtk_clk_mux_disable(clk);\n+}\n+\n static int mtk_common_clk_set_parent(struct clk *clk, struct clk *parent)\n {\n \tstruct mtk_clk_priv *parent_priv = dev_get_priv(parent->dev);\n \tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n \tu32 parent_type;\n \n-\tif (clk->id < priv->tree->muxes_offs)\n+\tif (!priv->tree->muxes || clk->id < priv->tree->muxes_offs ||\n+\t clk->id >= priv->tree->muxes_offs + priv->tree->num_muxes)\n \t\treturn 0;\n \n \tif (!parent_priv)\n@@ -821,6 +864,16 @@ static void mtk_topckgen_dump(struct udevice *dev)\n \t\tmtk_clk_print_mux_parents(priv, mux);\n \t\tprintf(\"\\n\");\n \t}\n+\n+\tfor (i = 0; i < tree->num_gates; i++) {\n+\t\tconst struct mtk_gate *gate = &tree->gates[i];\n+\n+\t\tprintf(\"[GATE%u] DT: %u\", i, gate->id);\n+\t\tmtk_clk_print_mapped_id(gate->id, i + tree->gates_offs, tree->id_offs_map);\n+\t\tmtk_clk_print_rate(dev, i + tree->gates_offs);\n+\t\tmtk_clk_print_single_parent(gate->parent, gate->flags);\n+\t\tprintf(\"\\n\");\n+\t}\n }\n #endif\n \n@@ -1124,8 +1177,8 @@ const struct clk_ops mtk_clk_fixed_pll_ops = {\n \n const struct clk_ops mtk_clk_topckgen_ops = {\n \t.of_xlate = mtk_topckgen_of_xlate,\n-\t.enable = mtk_clk_mux_enable,\n-\t.disable = mtk_clk_mux_disable,\n+\t.enable = mtk_topckgen_enable,\n+\t.disable = mtk_topckgen_disable,\n \t.get_rate = mtk_topckgen_get_rate,\n \t.set_parent = mtk_common_clk_set_parent,\n #if CONFIG_IS_ENABLED(CMD_CLK)\n","prefixes":["7/9"]}