{"id":2175771,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175771/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20251218213229.61854-2-philmd@linaro.org>","date":"2025-12-18T21:32:27","name":"[1/3] target/tricore: Use little-endian variant of cpu_ld/st_data*()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c76e6707043cef364ae79d4a9494ee9372e007ac","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/1.0/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20251218213229.61854-2-philmd@linaro.org/mbox/","series":[{"id":485920,"url":"http://patchwork.ozlabs.org/api/1.0/series/485920/?format=json","date":"2025-12-18T21:32:27","name":"target/tricore: Stop using the legacy native-endian APIs","version":1,"mbox":"http://patchwork.ozlabs.org/series/485920/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175771/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=C6k0yKgy;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::343;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x343.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"We only build the TriCore target using little endianness order,\ntherefore the cpu_ld/st_data*() definitions expand to the little\nendian declarations. Use the explicit little-endian variants.\n\nMechanical change running:\n\n $ tgt=tricore; \\\n end=le; \\\n for op in data mmuidx_ra; do \\\n for ac in uw sw l q; do \\\n sed -i -e \"s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/\" \\\n $(git grep -l cpu_ target/${tgt}/); \\\n done;\n for ac in w l q; do \\\n sed -i -e \"s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/\" \\\n $(git grep -l cpu_ target/${tgt}/); \\\n done;\n done\n\nThen adapting spaces style manually to pass checkpatch.pl.\n\nSigned-off-by: Philippe Mathieu-Daudé \nReviewed-by: Richard Henderson \n---\n target/tricore/op_helper.c | 152 ++++++++++++++++++-------------------\n 1 file changed, 76 insertions(+), 76 deletions(-)","diff":"diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c\nindex 2c8281a67e0..3cff5000c73 100644\n--- a/target/tricore/op_helper.c\n+++ b/target/tricore/op_helper.c\n@@ -2451,84 +2451,84 @@ static bool cdc_zero(uint32_t *psw)\n \n static void save_context_upper(CPUTriCoreState *env, uint32_t ea)\n {\n- cpu_stl_data(env, ea, env->PCXI);\n- cpu_stl_data(env, ea+4, psw_read(env));\n- cpu_stl_data(env, ea+8, env->gpr_a[10]);\n- cpu_stl_data(env, ea+12, env->gpr_a[11]);\n- cpu_stl_data(env, ea+16, env->gpr_d[8]);\n- cpu_stl_data(env, ea+20, env->gpr_d[9]);\n- cpu_stl_data(env, ea+24, env->gpr_d[10]);\n- cpu_stl_data(env, ea+28, env->gpr_d[11]);\n- cpu_stl_data(env, ea+32, env->gpr_a[12]);\n- cpu_stl_data(env, ea+36, env->gpr_a[13]);\n- cpu_stl_data(env, ea+40, env->gpr_a[14]);\n- cpu_stl_data(env, ea+44, env->gpr_a[15]);\n- cpu_stl_data(env, ea+48, env->gpr_d[12]);\n- cpu_stl_data(env, ea+52, env->gpr_d[13]);\n- cpu_stl_data(env, ea+56, env->gpr_d[14]);\n- cpu_stl_data(env, ea+60, env->gpr_d[15]);\n+ cpu_stl_le_data(env, ea, env->PCXI);\n+ cpu_stl_le_data(env, ea + 4, psw_read(env));\n+ cpu_stl_le_data(env, ea + 8, env->gpr_a[10]);\n+ cpu_stl_le_data(env, ea + 12, env->gpr_a[11]);\n+ cpu_stl_le_data(env, ea + 16, env->gpr_d[8]);\n+ cpu_stl_le_data(env, ea + 20, env->gpr_d[9]);\n+ cpu_stl_le_data(env, ea + 24, env->gpr_d[10]);\n+ cpu_stl_le_data(env, ea + 28, env->gpr_d[11]);\n+ cpu_stl_le_data(env, ea + 32, env->gpr_a[12]);\n+ cpu_stl_le_data(env, ea + 36, env->gpr_a[13]);\n+ cpu_stl_le_data(env, ea + 40, env->gpr_a[14]);\n+ cpu_stl_le_data(env, ea + 44, env->gpr_a[15]);\n+ cpu_stl_le_data(env, ea + 48, env->gpr_d[12]);\n+ cpu_stl_le_data(env, ea + 52, env->gpr_d[13]);\n+ cpu_stl_le_data(env, ea + 56, env->gpr_d[14]);\n+ cpu_stl_le_data(env, ea + 60, env->gpr_d[15]);\n }\n \n static void save_context_lower(CPUTriCoreState *env, uint32_t ea)\n {\n- cpu_stl_data(env, ea, env->PCXI);\n- cpu_stl_data(env, ea+4, env->gpr_a[11]);\n- cpu_stl_data(env, ea+8, env->gpr_a[2]);\n- cpu_stl_data(env, ea+12, env->gpr_a[3]);\n- cpu_stl_data(env, ea+16, env->gpr_d[0]);\n- cpu_stl_data(env, ea+20, env->gpr_d[1]);\n- cpu_stl_data(env, ea+24, env->gpr_d[2]);\n- cpu_stl_data(env, ea+28, env->gpr_d[3]);\n- cpu_stl_data(env, ea+32, env->gpr_a[4]);\n- cpu_stl_data(env, ea+36, env->gpr_a[5]);\n- cpu_stl_data(env, ea+40, env->gpr_a[6]);\n- cpu_stl_data(env, ea+44, env->gpr_a[7]);\n- cpu_stl_data(env, ea+48, env->gpr_d[4]);\n- cpu_stl_data(env, ea+52, env->gpr_d[5]);\n- cpu_stl_data(env, ea+56, env->gpr_d[6]);\n- cpu_stl_data(env, ea+60, env->gpr_d[7]);\n+ cpu_stl_le_data(env, ea, env->PCXI);\n+ cpu_stl_le_data(env, ea + 4, env->gpr_a[11]);\n+ cpu_stl_le_data(env, ea + 8, env->gpr_a[2]);\n+ cpu_stl_le_data(env, ea + 12, env->gpr_a[3]);\n+ cpu_stl_le_data(env, ea + 16, env->gpr_d[0]);\n+ cpu_stl_le_data(env, ea + 20, env->gpr_d[1]);\n+ cpu_stl_le_data(env, ea + 24, env->gpr_d[2]);\n+ cpu_stl_le_data(env, ea + 28, env->gpr_d[3]);\n+ cpu_stl_le_data(env, ea + 32, env->gpr_a[4]);\n+ cpu_stl_le_data(env, ea + 36, env->gpr_a[5]);\n+ cpu_stl_le_data(env, ea + 40, env->gpr_a[6]);\n+ cpu_stl_le_data(env, ea + 44, env->gpr_a[7]);\n+ cpu_stl_le_data(env, ea + 48, env->gpr_d[4]);\n+ cpu_stl_le_data(env, ea + 52, env->gpr_d[5]);\n+ cpu_stl_le_data(env, ea + 56, env->gpr_d[6]);\n+ cpu_stl_le_data(env, ea + 60, env->gpr_d[7]);\n }\n \n static void restore_context_upper(CPUTriCoreState *env, uint32_t ea,\n uint32_t *new_PCXI, uint32_t *new_PSW)\n {\n- *new_PCXI = cpu_ldl_data(env, ea);\n- *new_PSW = cpu_ldl_data(env, ea+4);\n- env->gpr_a[10] = cpu_ldl_data(env, ea+8);\n- env->gpr_a[11] = cpu_ldl_data(env, ea+12);\n- env->gpr_d[8] = cpu_ldl_data(env, ea+16);\n- env->gpr_d[9] = cpu_ldl_data(env, ea+20);\n- env->gpr_d[10] = cpu_ldl_data(env, ea+24);\n- env->gpr_d[11] = cpu_ldl_data(env, ea+28);\n- env->gpr_a[12] = cpu_ldl_data(env, ea+32);\n- env->gpr_a[13] = cpu_ldl_data(env, ea+36);\n- env->gpr_a[14] = cpu_ldl_data(env, ea+40);\n- env->gpr_a[15] = cpu_ldl_data(env, ea+44);\n- env->gpr_d[12] = cpu_ldl_data(env, ea+48);\n- env->gpr_d[13] = cpu_ldl_data(env, ea+52);\n- env->gpr_d[14] = cpu_ldl_data(env, ea+56);\n- env->gpr_d[15] = cpu_ldl_data(env, ea+60);\n+ *new_PCXI = cpu_ldl_le_data(env, ea);\n+ *new_PSW = cpu_ldl_le_data(env, ea + 4);\n+ env->gpr_a[10] = cpu_ldl_le_data(env, ea + 8);\n+ env->gpr_a[11] = cpu_ldl_le_data(env, ea + 12);\n+ env->gpr_d[8] = cpu_ldl_le_data(env, ea + 16);\n+ env->gpr_d[9] = cpu_ldl_le_data(env, ea + 20);\n+ env->gpr_d[10] = cpu_ldl_le_data(env, ea + 24);\n+ env->gpr_d[11] = cpu_ldl_le_data(env, ea + 28);\n+ env->gpr_a[12] = cpu_ldl_le_data(env, ea + 32);\n+ env->gpr_a[13] = cpu_ldl_le_data(env, ea + 36);\n+ env->gpr_a[14] = cpu_ldl_le_data(env, ea + 40);\n+ env->gpr_a[15] = cpu_ldl_le_data(env, ea + 44);\n+ env->gpr_d[12] = cpu_ldl_le_data(env, ea + 48);\n+ env->gpr_d[13] = cpu_ldl_le_data(env, ea + 52);\n+ env->gpr_d[14] = cpu_ldl_le_data(env, ea + 56);\n+ env->gpr_d[15] = cpu_ldl_le_data(env, ea + 60);\n }\n \n static void restore_context_lower(CPUTriCoreState *env, uint32_t ea,\n uint32_t *ra, uint32_t *pcxi)\n {\n- *pcxi = cpu_ldl_data(env, ea);\n- *ra = cpu_ldl_data(env, ea+4);\n- env->gpr_a[2] = cpu_ldl_data(env, ea+8);\n- env->gpr_a[3] = cpu_ldl_data(env, ea+12);\n- env->gpr_d[0] = cpu_ldl_data(env, ea+16);\n- env->gpr_d[1] = cpu_ldl_data(env, ea+20);\n- env->gpr_d[2] = cpu_ldl_data(env, ea+24);\n- env->gpr_d[3] = cpu_ldl_data(env, ea+28);\n- env->gpr_a[4] = cpu_ldl_data(env, ea+32);\n- env->gpr_a[5] = cpu_ldl_data(env, ea+36);\n- env->gpr_a[6] = cpu_ldl_data(env, ea+40);\n- env->gpr_a[7] = cpu_ldl_data(env, ea+44);\n- env->gpr_d[4] = cpu_ldl_data(env, ea+48);\n- env->gpr_d[5] = cpu_ldl_data(env, ea+52);\n- env->gpr_d[6] = cpu_ldl_data(env, ea+56);\n- env->gpr_d[7] = cpu_ldl_data(env, ea+60);\n+ *pcxi = cpu_ldl_le_data(env, ea);\n+ *ra = cpu_ldl_le_data(env, ea + 4);\n+ env->gpr_a[2] = cpu_ldl_le_data(env, ea + 8);\n+ env->gpr_a[3] = cpu_ldl_le_data(env, ea + 12);\n+ env->gpr_d[0] = cpu_ldl_le_data(env, ea + 16);\n+ env->gpr_d[1] = cpu_ldl_le_data(env, ea + 20);\n+ env->gpr_d[2] = cpu_ldl_le_data(env, ea + 24);\n+ env->gpr_d[3] = cpu_ldl_le_data(env, ea + 28);\n+ env->gpr_a[4] = cpu_ldl_le_data(env, ea + 32);\n+ env->gpr_a[5] = cpu_ldl_le_data(env, ea + 36);\n+ env->gpr_a[6] = cpu_ldl_le_data(env, ea + 40);\n+ env->gpr_a[7] = cpu_ldl_le_data(env, ea + 44);\n+ env->gpr_d[4] = cpu_ldl_le_data(env, ea + 48);\n+ env->gpr_d[5] = cpu_ldl_le_data(env, ea + 52);\n+ env->gpr_d[6] = cpu_ldl_le_data(env, ea + 56);\n+ env->gpr_d[7] = cpu_ldl_le_data(env, ea + 60);\n }\n \n void helper_call(CPUTriCoreState *env, uint32_t next_pc)\n@@ -2566,7 +2566,7 @@ void helper_call(CPUTriCoreState *env, uint32_t next_pc)\n ea = ((env->FCX & MASK_FCX_FCXS) << 12) +\n ((env->FCX & MASK_FCX_FCXO) << 6);\n /* new_FCX = M(EA, word); */\n- new_FCX = cpu_ldl_data(env, ea);\n+ new_FCX = cpu_ldl_le_data(env, ea);\n /* M(EA, 16 * word) = {PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11],\n A[12], A[13], A[14], A[15], D[12], D[13], D[14],\n D[15]}; */\n@@ -2632,7 +2632,7 @@ void helper_ret(CPUTriCoreState *env)\n A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */\n restore_context_upper(env, ea, &new_PCXI, &new_PSW);\n /* M(EA, word) = FCX; */\n- cpu_stl_data(env, ea, env->FCX);\n+ cpu_stl_le_data(env, ea, env->FCX);\n /* FCX[19: 0] = PCXI[19: 0]; */\n env->FCX = (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff);\n /* PCXI = new_PCXI; */\n@@ -2662,7 +2662,7 @@ void helper_bisr(CPUTriCoreState *env, uint32_t const9)\n ea = ((env->FCX & 0xf0000) << 12) + ((env->FCX & 0xffff) << 6);\n \n /* new_FCX = M(EA, word); */\n- new_FCX = cpu_ldl_data(env, ea);\n+ new_FCX = cpu_ldl_le_data(env, ea);\n /* M(EA, 16 * word) = {PCXI, A[11], A[2], A[3], D[0], D[1], D[2], D[3], A[4]\n , A[5], A[6], A[7], D[4], D[5], D[6], D[7]}; */\n save_context_lower(env, ea);\n@@ -2726,7 +2726,7 @@ void helper_rfe(CPUTriCoreState *env)\n A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */\n restore_context_upper(env, ea, &new_PCXI, &new_PSW);\n /* M(EA, word) = FCX;*/\n- cpu_stl_data(env, ea, env->FCX);\n+ cpu_stl_le_data(env, ea, env->FCX);\n /* FCX[19: 0] = PCXI[19: 0]; */\n env->FCX = (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff);\n /* PCXI = new_PCXI; */\n@@ -2744,10 +2744,10 @@ void helper_rfm(CPUTriCoreState *env)\n icr_set_ccpn(env, pcxi_get_pcpn(env));\n \n /* {PCXI, PSW, A[10], A[11]} = M(DCX, 4 * word); */\n- env->PCXI = cpu_ldl_data(env, env->DCX);\n- psw_write(env, cpu_ldl_data(env, env->DCX+4));\n- env->gpr_a[10] = cpu_ldl_data(env, env->DCX+8);\n- env->gpr_a[11] = cpu_ldl_data(env, env->DCX+12);\n+ env->PCXI = cpu_ldl_le_data(env, env->DCX);\n+ psw_write(env, cpu_ldl_le_data(env, env->DCX + 4));\n+ env->gpr_a[10] = cpu_ldl_le_data(env, env->DCX + 8);\n+ env->gpr_a[11] = cpu_ldl_le_data(env, env->DCX + 12);\n \n if (tricore_has_feature(env, TRICORE_FEATURE_131)) {\n env->DBGTCR = 0;\n@@ -2794,7 +2794,7 @@ void helper_svlcx(CPUTriCoreState *env)\n ea = ((env->FCX & MASK_FCX_FCXS) << 12) +\n ((env->FCX & MASK_FCX_FCXO) << 6);\n /* new_FCX = M(EA, word); */\n- new_FCX = cpu_ldl_data(env, ea);\n+ new_FCX = cpu_ldl_le_data(env, ea);\n /* M(EA, 16 * word) = {PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11],\n A[12], A[13], A[14], A[15], D[12], D[13], D[14],\n D[15]}; */\n@@ -2837,7 +2837,7 @@ void helper_svucx(CPUTriCoreState *env)\n ea = ((env->FCX & MASK_FCX_FCXS) << 12) +\n ((env->FCX & MASK_FCX_FCXO) << 6);\n /* new_FCX = M(EA, word); */\n- new_FCX = cpu_ldl_data(env, ea);\n+ new_FCX = cpu_ldl_le_data(env, ea);\n /* M(EA, 16 * word) = {PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11],\n A[12], A[13], A[14], A[15], D[12], D[13], D[14],\n D[15]}; */\n@@ -2887,9 +2887,9 @@ void helper_rslcx(CPUTriCoreState *env)\n A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */\n restore_context_lower(env, ea, &env->gpr_a[11], &new_PCXI);\n /* M(EA, word) = FCX; */\n- cpu_stl_data(env, ea, env->FCX);\n+ cpu_stl_le_data(env, ea, env->FCX);\n /* M(EA, word) = FCX; */\n- cpu_stl_data(env, ea, env->FCX);\n+ cpu_stl_le_data(env, ea, env->FCX);\n /* FCX[19: 0] = PCXI[19: 0]; */\n env->FCX = (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff);\n /* PCXI = new_PCXI; */\n","prefixes":["1/3"]}