{"id":2175763,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175763/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20251218212814.61445-2-philmd@linaro.org>","date":"2025-12-18T21:28:11","name":"[1/4] system/memory: Use explicit endianness in ram_device::read/write()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"347fe57967a5d4f99dc0ea5d7eec3ca2d37f1ff5","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/1.0/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20251218212814.61445-2-philmd@linaro.org/mbox/","series":[{"id":485917,"url":"http://patchwork.ozlabs.org/api/1.0/series/485917/?format=json","date":"2025-12-18T21:28:11","name":"system/memory: Allow restricting legacy 'native-endian' APIs","version":1,"mbox":"http://patchwork.ozlabs.org/series/485917/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175763/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=fOyXC9eW;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::429;\n envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Replace the ldn_he_p/stn_he_p() calls by their explicit endianness\nvariants. Duplicate the MemoryRegionOps, using one entry for BIG\nand another for LITTLE endianness. Select the proper MemoryRegionOps\nin memory_region_init_ram_device_ptr().\n\nSigned-off-by: Philippe Mathieu-Daudé \n---\n system/memory.c | 68 ++++++++++++++++++++++++++++++++++---------------\n 1 file changed, 48 insertions(+), 20 deletions(-)","diff":"diff --git a/system/memory.c b/system/memory.c\nindex 8b84661ae36..5bcdeaf0bee 100644\n--- a/system/memory.c\n+++ b/system/memory.c\n@@ -1361,41 +1361,69 @@ const MemoryRegionOps unassigned_mem_ops = {\n .endianness = DEVICE_NATIVE_ENDIAN,\n };\n \n-static uint64_t memory_region_ram_device_read(void *opaque,\n- hwaddr addr, unsigned size)\n+static uint64_t memory_region_ram_device_read_le(void *opaque,\n+ hwaddr addr, unsigned size)\n {\n MemoryRegion *mr = opaque;\n- uint64_t data = ldn_he_p(mr->ram_block->host + addr, size);\n+ uint64_t data = ldn_le_p(mr->ram_block->host + addr, size);\n \n trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);\n \n return data;\n }\n \n-static void memory_region_ram_device_write(void *opaque, hwaddr addr,\n- uint64_t data, unsigned size)\n+static uint64_t memory_region_ram_device_read_be(void *opaque,\n+ hwaddr addr, unsigned size)\n+{\n+ MemoryRegion *mr = opaque;\n+ uint64_t data = ldn_be_p(mr->ram_block->host + addr, size);\n+\n+ trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);\n+\n+ return data;\n+}\n+\n+static void memory_region_ram_device_write_le(void *opaque, hwaddr addr,\n+ uint64_t data, unsigned size)\n {\n MemoryRegion *mr = opaque;\n \n trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);\n \n- stn_he_p(mr->ram_block->host + addr, size, data);\n+ stn_le_p(mr->ram_block->host + addr, size, data);\n }\n \n-static const MemoryRegionOps ram_device_mem_ops = {\n- .read = memory_region_ram_device_read,\n- .write = memory_region_ram_device_write,\n- .endianness = HOST_BIG_ENDIAN ? DEVICE_BIG_ENDIAN : DEVICE_LITTLE_ENDIAN,\n- .valid = {\n- .min_access_size = 1,\n- .max_access_size = 8,\n- .unaligned = true,\n- },\n- .impl = {\n- .min_access_size = 1,\n- .max_access_size = 8,\n- .unaligned = true,\n+static void memory_region_ram_device_write_be(void *opaque, hwaddr addr,\n+ uint64_t data, unsigned size)\n+{\n+ MemoryRegion *mr = opaque;\n+\n+ trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);\n+\n+ stn_be_p(mr->ram_block->host + addr, size, data);\n+}\n+\n+static const MemoryRegionOps ram_device_mem_ops[2] = {\n+ [0 ... 1] = {\n+ .valid = {\n+ .min_access_size = 1,\n+ .max_access_size = 8,\n+ .unaligned = true,\n+ },\n+ .impl = {\n+ .min_access_size = 1,\n+ .max_access_size = 8,\n+ .unaligned = true,\n+ },\n },\n+\n+ [0].endianness = DEVICE_LITTLE_ENDIAN,\n+ [0].read = memory_region_ram_device_read_le,\n+ [0].write = memory_region_ram_device_write_le,\n+\n+ [1].endianness = DEVICE_BIG_ENDIAN,\n+ [1].read = memory_region_ram_device_read_be,\n+ [1].write = memory_region_ram_device_write_be,\n };\n \n bool memory_region_access_valid(MemoryRegion *mr,\n@@ -1712,7 +1740,7 @@ void memory_region_init_ram_device_ptr(MemoryRegion *mr,\n mr->ram = true;\n mr->terminates = true;\n mr->ram_device = true;\n- mr->ops = &ram_device_mem_ops;\n+ mr->ops = &ram_device_mem_ops[HOST_BIG_ENDIAN];\n mr->opaque = mr;\n mr->destructor = memory_region_destructor_ram;\n \n","prefixes":["1/4"]}