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CTRY:GB; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:outbound-uk1.az.dlp.m.darktrace.com;\n PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230040)(14060799003)(36860700013)(82310400026)(376014)(35042699022)(1800799024)(13003099007);\n DIR:OUT; SFP:1101;","X-OriginatorOrg":"arm.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"18 Dec 2025 21:13:00.1268 (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 035b7983-3bdf-4fdb-c785-08de3e7a394f","X-MS-Exchange-CrossTenant-Id":"f34e5979-57d9-4aaa-ad4d-b122a662184d","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n AMS0EPF000001A7.eurprd05.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list <gcc-patches.gcc.gnu.org>","List-Unsubscribe":"<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>","List-Archive":"<https://gcc.gnu.org/pipermail/gcc-patches/>","List-Post":"<mailto:gcc-patches@gcc.gnu.org>","List-Help":"<mailto:gcc-patches-request@gcc.gnu.org?subject=help>","List-Subscribe":"<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"New tests verify that GCC can generate predicated vector-length\nspecific code for AArch64 if the specified vector length is\nshorter than, equal to, or longer than the number of elements to\nbe processed (including if the specified length is sufficient but\nthe minimum length would not be); other tests verify that GCC can\ngenerate predicated vector-length agnostic code for AArch64 if\nthe minimum length (of 16 bytes) is shorter than, equal to, or\nlonger than the number of elements to be processed.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/sve/slp_pred_1.c: New test.\n\t* gcc.target/aarch64/sve/slp_pred_1_run.c: New test.\n\t* gcc.target/aarch64/sve/slp_pred_2.c: New test.\n\t* gcc.target/aarch64/sve/slp_pred_3.c: New test.\n\t* gcc.target/aarch64/sve/slp_pred_3_run.c: New test.\n\t* gcc.target/aarch64/sve/slp_pred_4.c: New test.\n\t* gcc.target/aarch64/sve/slp_pred_5.c: New test.\n\t* gcc.target/aarch64/sve/slp_pred_6.c: New test.\n\t* gcc.target/aarch64/sve/slp_pred_6_run.c: New test.\n\t* gcc.target/aarch64/sve/slp_pred_7.c: New test.\n\t* gcc.target/aarch64/sve/slp_pred_harness.h: Test harness\n\tshared between tests for vectorization with SVE predication.\n\n---\n .../gcc.target/aarch64/sve/slp_pred_1.c       | 33 ++++++++++++++++\n .../gcc.target/aarch64/sve/slp_pred_1_run.c   |  6 +++\n .../gcc.target/aarch64/sve/slp_pred_2.c       | 33 ++++++++++++++++\n .../gcc.target/aarch64/sve/slp_pred_3.c       | 33 ++++++++++++++++\n .../gcc.target/aarch64/sve/slp_pred_3_run.c   |  6 +++\n .../gcc.target/aarch64/sve/slp_pred_4.c       | 33 ++++++++++++++++\n .../gcc.target/aarch64/sve/slp_pred_5.c       | 36 +++++++++++++++++\n .../gcc.target/aarch64/sve/slp_pred_6.c       | 39 +++++++++++++++++++\n .../gcc.target/aarch64/sve/slp_pred_6_run.c   |  6 +++\n .../gcc.target/aarch64/sve/slp_pred_7.c       | 38 ++++++++++++++++++\n .../gcc.target/aarch64/sve/slp_pred_harness.h | 28 +++++++++++++\n 11 files changed, 291 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/slp_pred_1.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/slp_pred_1_run.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/slp_pred_2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/slp_pred_3.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/slp_pred_3_run.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/slp_pred_4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/slp_pred_5.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/slp_pred_6.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/slp_pred_6_run.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/slp_pred_7.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/slp_pred_harness.h","diff":"diff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_1.c b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_1.c\nnew file mode 100644\nindex 00000000000..4e0a78de02a\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_1.c\n@@ -0,0 +1,33 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -ftree-vectorize -march=armv9-a+sve --param=aarch64-autovec-preference=sve-only -msve-vector-bits=scalable\" } */\n+\n+#include <stdint.h>\n+\n+/* Test that we can vectorize with SVE predication when generating vector-length\n+   agnostic code if the minimum possible vector length (of 16 bytes) is larger\n+   than the number of elements to be processed.  */\n+\n+void\n+f (uint8_t *x)\n+{\n+  x[0] += 1;\n+  x[1] += 2;\n+  x[2] += 1;\n+  x[3] += 2;\n+  x[4] += 1;\n+  x[5] += 2;\n+  x[6] += 1;\n+  x[7] += 2;\n+  x[8] += 1;\n+  x[9] += 2;\n+  x[10] += 1;\n+  x[11] += 2;\n+  x[12] += 1;\n+  x[13] += 2;\n+  x[14] += 1; // one less than the minimum vector length\n+}\n+\n+/* { dg-final { scan-assembler-times {\\twhilelo\\tp[0-7].b, xzr, x[0-9]\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tld1b\\tz[0-9]+\\.b, p[0-7]/z, \\[x[0-9]\\]\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tadd\\tz[0-9]+\\.b, z[0-9]+\\.b, z[0-9]+\\.b\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tst1b\\tz[0-9]+\\.b, p[0-7], \\[x[0-9]\\]\\n} 1 } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_1_run.c b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_1_run.c\nnew file mode 100644\nindex 00000000000..7d0a88fec2f\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_1_run.c\n@@ -0,0 +1,6 @@\n+/* { dg-do run { target aarch64_sve_hw } } */\n+/* { dg-options \"-O2 -ftree-vectorize -march=armv9-a+sve --param=aarch64-autovec-preference=sve-only -msve-vector-bits=scalable\" } */\n+#include \"slp_pred_harness.h\"\n+#include \"slp_pred_1.c\"\n+\n+HARNESS (15)\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_2.c b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_2.c\nnew file mode 100644\nindex 00000000000..da120ad36f9\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_2.c\n@@ -0,0 +1,33 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -ftree-vectorize -march=armv9-a+sve --param=aarch64-autovec-preference=sve-only -msve-vector-bits=128\" } */\n+\n+#include <stdint.h>\n+\n+/* Test that we can vectorize with SVE predication when generating vector-length\n+   specific code if the configured vector length is larger than the number of\n+   elements to be processed.  */\n+\n+void\n+f (uint8_t *x)\n+{\n+  x[0] += 1;\n+  x[1] += 2;\n+  x[2] += 1;\n+  x[3] += 2;\n+  x[4] += 1;\n+  x[5] += 2;\n+  x[6] += 1;\n+  x[7] += 2;\n+  x[8] += 1;\n+  x[9] += 2;\n+  x[10] += 1;\n+  x[11] += 2;\n+  x[12] += 1;\n+  x[13] += 2;\n+  x[14] += 1; // one less than the configured vector length\n+}\n+\n+/* { dg-final { scan-assembler-times {\\tptrue\\tp[0-7].b, mul3\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tld1b\\tz[0-9]+\\.b, p[0-7]/z, \\[x[0-9]\\]\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tadd\\tz[0-9]+\\.b, z[0-9]+\\.b, z[0-9]+\\.b\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tst1b\\tz[0-9]+\\.b, p[0-7], \\[x[0-9]\\]\\n} 1 } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_3.c b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_3.c\nnew file mode 100644\nindex 00000000000..184b9615cd9\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_3.c\n@@ -0,0 +1,33 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -ftree-vectorize -march=armv9-a+sve --param=aarch64-autovec-preference=sve-only -msve-vector-bits=scalable\" } */\n+\n+#include <stdint.h>\n+\n+/* Test that we can vectorize with SVE predication when generating vector-length\n+   agnostic code if the minimum possible vector length (of 16 bytes) is equal to\n+   the number of elements to be processed.  */\n+\n+void\n+f (uint8_t *x)\n+{\n+  x[0] += 1;\n+  x[1] += 2;\n+  x[2] += 1;\n+  x[3] += 2;\n+  x[4] += 1;\n+  x[5] += 2;\n+  x[6] += 1;\n+  x[7] += 2;\n+  x[8] += 1;\n+  x[9] += 2;\n+  x[10] += 1;\n+  x[11] += 2;\n+  x[12] += 1;\n+  x[13] += 2;\n+  x[14] += 1;\n+  x[15] += 2; // exactly fits the minimum vector length\n+}\n+\n+/* { dg-final { scan-assembler-times {\\tldr\\tq[0-9]+, \\[x[0-9]\\]\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tadd\\tz[0-9]+\\.b, z[0-9]+\\.b, z[0-9]+\\.b\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tstr\\tq[0-9]+, \\[x[0-9]\\]\\n} 1 } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_3_run.c b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_3_run.c\nnew file mode 100644\nindex 00000000000..5c92b1e0b39\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_3_run.c\n@@ -0,0 +1,6 @@\n+/* { dg-do run { target aarch64_sve_hw } } */\n+/* { dg-options \"-O2 -ftree-vectorize -march=armv9-a+sve --param=aarch64-autovec-preference=sve-only -msve-vector-bits=scalable\" } */\n+#include \"slp_pred_harness.h\"\n+#include \"slp_pred_3.c\"\n+\n+HARNESS (16)\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_4.c b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_4.c\nnew file mode 100644\nindex 00000000000..ecb6ee2304a\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_4.c\n@@ -0,0 +1,33 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -ftree-vectorize -march=armv9-a+sve --param=aarch64-autovec-preference=sve-only -msve-vector-bits=128\" } */\n+\n+#include <stdint.h>\n+\n+/* Test that we can vectorize with SVE predication when generating vector-length\n+   specific code if the configured vector length is equal to the number of\n+   elements to be processed.  */\n+\n+void\n+f (uint8_t *x)\n+{\n+  x[0] += 1;\n+  x[1] += 2;\n+  x[2] += 1;\n+  x[3] += 2;\n+  x[4] += 1;\n+  x[5] += 2;\n+  x[6] += 1;\n+  x[7] += 2;\n+  x[8] += 1;\n+  x[9] += 2;\n+  x[10] += 1;\n+  x[11] += 2;\n+  x[12] += 1;\n+  x[13] += 2;\n+  x[14] += 1;\n+  x[15] += 2; // exactly fits the configured vector length\n+}\n+\n+/* { dg-final { scan-assembler-times {\\tldr\\tq[0-9]+, \\[x[0-9]\\]\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tadd\\tz[0-9]+\\.b, z[0-9]+\\.b, z[0-9]+\\.b\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tstr\\tq[0-9]+, \\[x[0-9]\\]\\n} 1 } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_5.c b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_5.c\nnew file mode 100644\nindex 00000000000..076756ff948\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_5.c\n@@ -0,0 +1,36 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -ftree-vectorize -march=armv9-a+sve --param=aarch64-autovec-preference=sve-only -msve-vector-bits=256\" } */\n+\n+#include <stdint.h>\n+\n+/* Test that we can vectorize with SVE predication when generating\n+   vector-length specific code if the number of elements to be\n+   processed is greater than the minimum possible vector length\n+   (of 16 bytes) but less the configured vector length.  */\n+\n+void\n+f (uint8_t *x)\n+{\n+  x[0] += 1;\n+  x[1] += 2;\n+  x[2] += 1;\n+  x[3] += 2;\n+  x[4] += 1;\n+  x[5] += 2;\n+  x[6] += 1;\n+  x[7] += 2;\n+  x[8] += 1;\n+  x[9] += 2;\n+  x[10] += 1;\n+  x[11] += 2;\n+  x[12] += 1;\n+  x[13] += 2;\n+  x[14] += 1;\n+  x[15] += 2;\n+  x[16] += 1; // one more than the minimum vector length\n+}\n+\n+/* { dg-final { scan-assembler-times {\\twhilelo\\tp[0-7].b, xzr, x[0-9]+\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tld1b\\tz[0-9]+\\.b, p[0-7]/z, \\[x[0-9]+\\]\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tadd\\tz[0-9]+\\.b, z[0-9]+\\.b, z[0-9]+\\.b\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tst1b\\tz[0-9]+\\.b, p[0-7], \\[x[0-9]+\\]\\n} 1 } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_6.c b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_6.c\nnew file mode 100644\nindex 00000000000..fffb52e8f4b\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_6.c\n@@ -0,0 +1,39 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -ftree-vectorize -march=armv9-a+sve --param=aarch64-autovec-preference=sve-only -msve-vector-bits=scalable\" } */\n+\n+#include <stdint.h>\n+\n+/* Test that we do not attempt to vectorize with SVE predication when\n+   generating vector-length agnostic code if the minimum possible\n+   vector length (of 16 bytes) is smaller than the number of elements\n+   to be processed.  */\n+\n+void\n+f (uint8_t *x)\n+{\n+  x[0] += 1;\n+  x[1] += 2;\n+  x[2] += 1;\n+  x[3] += 2;\n+  x[4] += 1;\n+  x[5] += 2;\n+  x[6] += 1;\n+  x[7] += 2;\n+  x[8] += 1;\n+  x[9] += 2;\n+  x[10] += 1;\n+  x[11] += 2;\n+  x[12] += 1;\n+  x[13] += 2;\n+  x[14] += 1;\n+  x[15] += 2;\n+  x[16] += 1; // one more than the minimum vector length\n+}\n+\n+/* { dg-final { scan-assembler-times {\\tldr\\tq[0-9]+, \\[x[0-9]\\]\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tadd\\tz[0-9]+\\.b, z[0-9]+\\.b, z[0-9]+\\.b\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tstr\\tq[0-9]+, \\[x[0-9]\\]\\n} 1 } } */\n+\n+/* { dg-final { scan-assembler-times {\\tldrb\\tw[0-9]+, \\[x[0-9], 16\\]\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tadd\\tw[0-9]+, w[0-9]+, 1\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tstrb\\tw[0-9]+, \\[x[0-9], 16\\]\\n} 1 } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_6_run.c b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_6_run.c\nnew file mode 100644\nindex 00000000000..2147a66abe9\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_6_run.c\n@@ -0,0 +1,6 @@\n+/* { dg-do run { target aarch64_sve_hw } } */\n+/* { dg-options \"-O2 -ftree-vectorize -march=armv9-a+sve --param=aarch64-autovec-preference=sve-only -msve-vector-bits=scalable\" } */\n+#include \"slp_pred_harness.h\"\n+#include \"slp_pred_6.c\"\n+\n+HARNESS (17)\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_7.c b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_7.c\nnew file mode 100644\nindex 00000000000..82f744c8bbc\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_7.c\n@@ -0,0 +1,38 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -ftree-vectorize -march=armv9-a+sve --param=aarch64-autovec-preference=sve-only -msve-vector-bits=128\" } */\n+\n+#include <stdint.h>\n+\n+/* Test that we do not attempt to vectorize with SVE predication when\n+   generating vector-length specific code if the configured vector\n+   length is smaller than the number of elements to be processed.  */\n+\n+void\n+f (uint8_t *x)\n+{\n+  x[0] += 1;\n+  x[1] += 2;\n+  x[2] += 1;\n+  x[3] += 2;\n+  x[4] += 1;\n+  x[5] += 2;\n+  x[6] += 1;\n+  x[7] += 2;\n+  x[8] += 1;\n+  x[9] += 2;\n+  x[10] += 1;\n+  x[11] += 2;\n+  x[12] += 1;\n+  x[13] += 2;\n+  x[14] += 1;\n+  x[15] += 2;\n+  x[16] += 1; // one more than the configured vector length\n+}\n+\n+/* { dg-final { scan-assembler-times {\\tldr\\tq[0-9]+, \\[x[0-9]\\]\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tadd\\tz[0-9]+\\.b, z[0-9]+\\.b, z[0-9]+\\.b\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tstr\\tq[0-9]+, \\[x[0-9]\\]\\n} 1 } } */\n+\n+/* { dg-final { scan-assembler-times {\\tldrb\\tw[0-9]+, \\[x[0-9], 16\\]\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tadd\\tw[0-9]+, w[0-9]+, 1\\n} 1 } } */\n+/* { dg-final { scan-assembler-times {\\tstrb\\tw[0-9]+, \\[x[0-9], 16\\]\\n} 1 } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_harness.h b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_harness.h\nnew file mode 100644\nindex 00000000000..ac569fc670c\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_pred_harness.h\n@@ -0,0 +1,28 @@\n+/* Test harness shared between tests for vectorization with SVE predication.  */\n+\n+#define HARNESS(N)                                                             \\\n+  int __attribute__ ((optimize (1))) main (void)                               \\\n+  {                                                                            \\\n+    uint8_t a[N], b[N];                                                        \\\n+    for (unsigned int i = 0; i < N; ++i)                                       \\\n+      {                                                                        \\\n+\ta[i] = i * 2 + i % 5;                                                  \\\n+\tb[i] = a[i];                                                           \\\n+\tasm volatile (\"\" ::: \"memory\");                                        \\\n+      }                                                                        \\\n+    f (a);                                                                     \\\n+    for (unsigned int i = 0; i < N; i += 2)                                    \\\n+      {                                                                        \\\n+\tb[i]++;                                                                \\\n+\tif (a[i] != b[i])                                                      \\\n+\t  __builtin_abort ();                                                  \\\n+\tif (i + 1 < N)                                                         \\\n+\t  {                                                                    \\\n+\t    b[i + 1] += 2;                                                     \\\n+\t    if (a[i + 1] != b[i + 1])                                          \\\n+\t      __builtin_abort ();                                              \\\n+\t  }                                                                    \\\n+\tasm volatile (\"\" ::: \"memory\");                                        \\\n+      }                                                                        \\\n+    return 0;                                                                  \\\n+  }\n","prefixes":["v7","09/10"]}