{"id":2175734,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175734/?format=json","project":{"id":69,"url":"http://patchwork.ozlabs.org/api/1.0/projects/69/?format=json","name":"QEMU powerpc development","link_name":"qemu-ppc","list_id":"qemu-ppc.nongnu.org","list_email":"qemu-ppc@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20251218200353.301866-5-calebs@linux.ibm.com>","date":"2025-12-18T20:03:53","name":"[4/4] ppc/pnv: Add OCC FLAG registers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"9de0d04b118ea53f7b2f234192c82cd1d365c7be","submitter":{"id":90855,"url":"http://patchwork.ozlabs.org/api/1.0/people/90855/?format=json","name":"Caleb Schlossin","email":"calebs@linux.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-ppc/patch/20251218200353.301866-5-calebs@linux.ibm.com/mbox/","series":[{"id":485909,"url":"http://patchwork.ozlabs.org/api/1.0/series/485909/?format=json","date":"2025-12-18T20:03:52","name":"Power10 PowerVM bringup fixes","version":1,"mbox":"http://patchwork.ozlabs.org/series/485909/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175734/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=Mx0YuxQG;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n 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DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7,\n RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-ppc@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"OCCFLG are scratch registers that can be shared with OCC firmware.\nLog reads and writes to the registers as a reminder when we run\ninto more OCC code.\n\nAdd RW, WO_CLEAR and WO_OR SCOM Type enums in pnv_occ.c\n\nSigned-off-by: Chalapathi V \nSigned-off-by: Caleb Schlossin \n---\n hw/ppc/pnv_occ.c | 55 +++++++++++++++++++++++++++++++++++++---\n include/hw/ppc/pnv_occ.h | 4 +++\n 2 files changed, 56 insertions(+), 3 deletions(-)","diff":"diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c\nindex 24b789c191..e605ae0fbc 100644\n--- a/hw/ppc/pnv_occ.c\n+++ b/hw/ppc/pnv_occ.c\n@@ -195,6 +195,49 @@ static const TypeInfo pnv_occ_power8_type_info = {\n #define P9_OCB_OCI_OCCMISC_CLEAR 0x6081\n #define P9_OCB_OCI_OCCMISC_OR 0x6082\n \n+/* OCC scratch registers for flag setting */\n+#define P9_OCCFLG0 0x60ac\n+#define P9_OCCFLG7_OR 0x60c3\n+\n+enum ScomType {\n+ SCOM_TYPE_RW = 0,\n+ SCOM_TYPE_WO_CLEAR = 1,\n+ SCOM_TYPE_WO_OR = 2,\n+};\n+\n+static void rw_occ_flag_regs(PnvOCC *occ, uint32_t offset, bool read,\n+ uint64_t *val)\n+{\n+ int flag_num;\n+ int flag_type;\n+\n+ /*\n+ * Each OCCFLG register has SCOM0 - RW, SCOM1 - WO_CLEAR, SCOM2 - WO_OR\n+ * hence devide by 3 to get flag index and mod 3 to get SCOM type.\n+ */\n+ flag_num = (offset - P9_OCCFLG0) / 3;\n+ flag_type = (offset - P9_OCCFLG0) % 3;\n+\n+ if (read) {\n+ if (flag_type) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"OCC: Write only register: Ox%\"\n+ PRIx32 \"\\n\", offset);\n+ return;\n+ }\n+ *val = occ->occflags[flag_num];\n+ } else {\n+ switch (flag_type) {\n+ case SCOM_TYPE_RW:\n+ occ->occflags[flag_num] = *val;\n+ break;\n+ case SCOM_TYPE_WO_CLEAR:\n+ occ->occflags[flag_num] &= ~(*val);\n+ break;\n+ case SCOM_TYPE_WO_OR:\n+ occ->occflags[flag_num] |= *val;\n+ }\n+ }\n+}\n \n static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,\n unsigned size)\n@@ -207,8 +250,11 @@ static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,\n case P9_OCB_OCI_OCCMISC:\n val = occ->occmisc;\n break;\n+ case P9_OCCFLG0 ... P9_OCCFLG7_OR:\n+ rw_occ_flag_regs(occ, offset, 1, &val);\n+ break;\n default:\n- qemu_log_mask(LOG_UNIMP, \"OCC Unimplemented register: Ox%\"\n+ qemu_log_mask(LOG_UNIMP, \"OCC Unimplemented register read: Ox%\"\n HWADDR_PRIx \"\\n\", addr >> 3);\n }\n return val;\n@@ -229,9 +275,12 @@ static void pnv_occ_power9_xscom_write(void *opaque, hwaddr addr,\n break;\n case P9_OCB_OCI_OCCMISC:\n pnv_occ_set_misc(occ, val);\n- break;\n+ break;\n+ case P9_OCCFLG0 ... P9_OCCFLG7_OR:\n+ rw_occ_flag_regs(occ, offset, 0, &val);\n+ break;\n default:\n- qemu_log_mask(LOG_UNIMP, \"OCC Unimplemented register: Ox%\"\n+ qemu_log_mask(LOG_UNIMP, \"OCC Unimplemented register write: Ox%\"\n HWADDR_PRIx \"\\n\", addr >> 3);\n }\n }\ndiff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h\nindex 013ea2e53e..8c9f1416eb 100644\n--- a/include/hw/ppc/pnv_occ.h\n+++ b/include/hw/ppc/pnv_occ.h\n@@ -47,6 +47,10 @@ struct PnvOCC {\n /* OCC Misc interrupt */\n uint64_t occmisc;\n \n+ /* OCC Flags */\n+#define NR_FLAG_REGS 8\n+ uint32_t occflags[NR_FLAG_REGS];\n+\n qemu_irq psi_irq;\n \n /* OCCs operate on regions of HOMER memory */\n","prefixes":["4/4"]}