{"id":2175699,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175699/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20251218183122.408690-4-sergeev0xef@gmail.com>","date":"2025-12-18T18:31:18","name":"[RFC,3/6] target/riscv: Get rid of hardcoded SBI events.","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e6c71cd22afff707a28f3f1c67e8b3a89b1a49be","submitter":{"id":92294,"url":"http://patchwork.ozlabs.org/api/1.0/people/92294/?format=json","name":"Aleksandr Sergeev","email":"sergeev0xef@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20251218183122.408690-4-sergeev0xef@gmail.com/mbox/","series":[{"id":485896,"url":"http://patchwork.ozlabs.org/api/1.0/series/485896/?format=json","date":"2025-12-18T18:31:20","name":"More extendable PMU subsystem.","version":1,"mbox":"http://patchwork.ozlabs.org/series/485896/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175699/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=VtPvLXMJ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n 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events.","Date":"Thu, 18 Dec 2025 21:31:18 +0300","Message-ID":"<20251218183122.408690-4-sergeev0xef@gmail.com>","X-Mailer":"git-send-email 2.51.0","In-Reply-To":"<20251218183122.408690-1-sergeev0xef@gmail.com>","References":"<20251218183122.408690-1-sergeev0xef@gmail.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::12e;\n envelope-from=sergeev0xef@gmail.com; helo=mail-lf1-x12e.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-Mailman-Approved-At":"Thu, 18 Dec 2025 13:32:44 -0500","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"SBI events are not a part of RISC-V specification\nand should not be hardcoded right in QEMU.\nIt's up to vendor to implement them.\n\nAlso, we can get rid of event->ctr mapping,\nas it is used only for SBI event handling.\n\nSigned-off-by: Aleksandr Sergeev \nReviewed-by: Alexei Filippov \n---\n target/riscv/cpu.h | 15 ---\n target/riscv/cpu_helper.c | 23 ----\n target/riscv/csr.c | 18 +--\n target/riscv/pmu.c | 240 ++------------------------------------\n target/riscv/pmu.h | 7 --\n 5 files changed, 16 insertions(+), 287 deletions(-)","diff":"diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 36e7f10037..8ab5fa0afb 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -550,8 +550,6 @@ struct ArchCPU {\n QEMUTimer *pmu_timer;\n /* A bitmask of Available programmable counters */\n uint32_t pmu_avail_ctrs;\n- /* Mapping of events to counters */\n- GHashTable *pmu_event_ctr_map;\n const GPtrArray *decoders;\n };\n \n@@ -925,19 +923,6 @@ enum {\n CSR_TABLE_SIZE = 0x1000\n };\n \n-/*\n- * The event id are encoded based on the encoding specified in the\n- * SBI specification v0.3\n- */\n-\n-enum riscv_pmu_event_idx {\n- RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01,\n- RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02,\n- RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019,\n- RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B,\n- RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,\n-};\n-\n /* used by tcg/tcg-cpu.c*/\n void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);\n bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);\ndiff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c\nindex c4fb68b5de..b3780cf8a8 100644\n--- a/target/riscv/cpu_helper.c\n+++ b/target/riscv/cpu_helper.c\n@@ -1736,28 +1736,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,\n cpu_loop_exit_restore(cs, retaddr);\n }\n \n-\n-static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type)\n-{\n- enum riscv_pmu_event_idx pmu_event_type;\n-\n- switch (access_type) {\n- case MMU_INST_FETCH:\n- pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS;\n- break;\n- case MMU_DATA_LOAD:\n- pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS;\n- break;\n- case MMU_DATA_STORE:\n- pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS;\n- break;\n- default:\n- return;\n- }\n-\n- riscv_pmu_incr_ctr(cpu, pmu_event_type);\n-}\n-\n bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n MMUAccessType access_type, int mmu_idx,\n bool probe, uintptr_t retaddr)\n@@ -1781,7 +1759,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n qemu_log_mask(CPU_LOG_MMU, \"%s ad %\" VADDR_PRIx \" rw %d mmu_idx %d\\n\",\n __func__, address, access_type, mmu_idx);\n \n- pmu_tlb_fill_incr_ctr(cpu, access_type);\n if (two_stage_lookup) {\n /* Two stage lookup */\n ret = get_physical_address(env, &pa, &prot, address,\ndiff --git a/target/riscv/csr.c b/target/riscv/csr.c\nindex 81475ec9a3..fb052725fe 100644\n--- a/target/riscv/csr.c\n+++ b/target/riscv/csr.c\n@@ -1188,8 +1188,6 @@ static RISCVException write_mhpmevent(CPURISCVState *env, int csrno,\n env->mhpmevent_val[ctr_idx] = mhpmevt_val;\n }\n \n- riscv_pmu_update_event_map(env, mhpmevt_val, ctr_idx);\n-\n return RISCV_EXCP_NONE;\n }\n \n@@ -1223,8 +1221,6 @@ static RISCVException write_mhpmeventh(CPURISCVState *env, int csrno,\n mhpmevt_val = mhpmevt_val | (mhpmevth_val << 32);\n env->mhpmeventh_val[ctr_idx] = mhpmevth_val;\n \n- riscv_pmu_update_event_map(env, mhpmevt_val, ctr_idx);\n-\n return RISCV_EXCP_NONE;\n }\n \n@@ -1232,7 +1228,7 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *env,\n int counter_idx,\n bool upper_half)\n {\n- int inst = riscv_pmu_ctr_monitor_instructions(env, counter_idx);\n+ int inst = (counter_idx == HPM_MINSTRET_IDX);\n uint64_t *counter_arr_virt = env->pmu_fixed_ctrs[inst].counter_virt;\n uint64_t *counter_arr = env->pmu_fixed_ctrs[inst].counter;\n target_ulong result = 0;\n@@ -1303,8 +1299,7 @@ static RISCVException riscv_pmu_write_ctr(CPURISCVState *env, target_ulong val,\n \n counter->mhpmcounter_val = val;\n if (!get_field(env->mcountinhibit, BIT(ctr_idx)) &&\n- (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||\n- riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) {\n+ (ctr_idx == HPM_MCYCLE_IDX || ctr_idx == HPM_MINSTRET_IDX)) {\n counter->mhpmcounter_prev = riscv_pmu_ctr_get_fixed_counters_val(env,\n ctr_idx, false);\n if (ctr_idx > 2) {\n@@ -1332,8 +1327,7 @@ static RISCVException riscv_pmu_write_ctrh(CPURISCVState *env, target_ulong val,\n counter->mhpmcounterh_val = val;\n mhpmctr_val = mhpmctr_val | (mhpmctrh_val << 32);\n if (!get_field(env->mcountinhibit, BIT(ctr_idx)) &&\n- (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||\n- riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) {\n+ (ctr_idx == HPM_MCYCLE_IDX || ctr_idx == HPM_MINSTRET_IDX)) {\n counter->mhpmcounterh_prev = riscv_pmu_ctr_get_fixed_counters_val(env,\n ctr_idx, true);\n if (ctr_idx > 2) {\n@@ -1384,8 +1378,7 @@ RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,\n * The kernel computes the perf delta by subtracting the current value from\n * the value it initialized previously (ctr_val).\n */\n- if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||\n- riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {\n+ if (ctr_idx == HPM_MCYCLE_IDX || ctr_idx == HPM_MINSTRET_IDX) {\n *val = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx, upper_half) -\n ctr_prev + ctr_val;\n } else {\n@@ -2955,8 +2948,7 @@ static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,\n /* Check if any other counter is also monitoring cycles/instructions */\n for (cidx = 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) {\n if (!(updated_ctrs & BIT(cidx)) ||\n- (!riscv_pmu_ctr_monitor_cycles(env, cidx) &&\n- !riscv_pmu_ctr_monitor_instructions(env, cidx))) {\n+ (cidx != HPM_MCYCLE_IDX && cidx != HPM_MINSTRET_IDX)) {\n continue;\n }\n \ndiff --git a/target/riscv/pmu.c b/target/riscv/pmu.c\nindex b983eadd83..c503fffde1 100644\n--- a/target/riscv/pmu.c\n+++ b/target/riscv/pmu.c\n@@ -101,82 +101,6 @@ static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, uint32_t ctr_idx)\n }\n }\n \n-static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx)\n-{\n- CPURISCVState *env = &cpu->env;\n- target_ulong max_val = UINT32_MAX;\n- PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];\n- bool virt_on = env->virt_enabled;\n-\n- /* Privilege mode filtering */\n- if ((env->priv == PRV_M &&\n- (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_MINH)) ||\n- (env->priv == PRV_S && virt_on &&\n- (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VSINH)) ||\n- (env->priv == PRV_U && virt_on &&\n- (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VUINH)) ||\n- (env->priv == PRV_S && !virt_on &&\n- (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_SINH)) ||\n- (env->priv == PRV_U && !virt_on &&\n- (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_UINH))) {\n- return 0;\n- }\n-\n- /* Handle the overflow scenario */\n- if (counter->mhpmcounter_val == max_val) {\n- if (counter->mhpmcounterh_val == max_val) {\n- counter->mhpmcounter_val = 0;\n- counter->mhpmcounterh_val = 0;\n- /* Generate interrupt only if OF bit is clear */\n- if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) {\n- env->mhpmeventh_val[ctr_idx] |= MHPMEVENTH_BIT_OF;\n- riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));\n- }\n- } else {\n- counter->mhpmcounterh_val++;\n- }\n- } else {\n- counter->mhpmcounter_val++;\n- }\n-\n- return 0;\n-}\n-\n-static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx)\n-{\n- CPURISCVState *env = &cpu->env;\n- PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];\n- uint64_t max_val = UINT64_MAX;\n- bool virt_on = env->virt_enabled;\n-\n- /* Privilege mode filtering */\n- if ((env->priv == PRV_M &&\n- (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) ||\n- (env->priv == PRV_S && virt_on &&\n- (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VSINH)) ||\n- (env->priv == PRV_U && virt_on &&\n- (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VUINH)) ||\n- (env->priv == PRV_S && !virt_on &&\n- (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) ||\n- (env->priv == PRV_U && !virt_on &&\n- (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) {\n- return 0;\n- }\n-\n- /* Handle the overflow scenario */\n- if (counter->mhpmcounter_val == max_val) {\n- counter->mhpmcounter_val = 0;\n- /* Generate interrupt only if OF bit is clear */\n- if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) {\n- env->mhpmevent_val[ctr_idx] |= MHPMEVENT_BIT_OF;\n- riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));\n- }\n- } else {\n- counter->mhpmcounter_val++;\n- }\n- return 0;\n-}\n-\n /*\n * Information needed to update counters:\n * new_priv, new_virt: To correctly save starting snapshot for the newly\n@@ -272,97 +196,6 @@ void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv,\n riscv_pmu_icount_update_priv(env, newpriv, new_virt);\n }\n \n-int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx)\n-{\n- uint32_t ctr_idx;\n- int ret;\n- CPURISCVState *env = &cpu->env;\n- gpointer value;\n-\n- if (!cpu->cfg.pmu_mask) {\n- return 0;\n- }\n- value = g_hash_table_lookup(cpu->pmu_event_ctr_map,\n- GUINT_TO_POINTER(event_idx));\n- if (!value) {\n- return -1;\n- }\n-\n- ctr_idx = GPOINTER_TO_UINT(value);\n- if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) {\n- return -1;\n- }\n-\n- if (riscv_cpu_mxl(env) == MXL_RV32) {\n- ret = riscv_pmu_incr_ctr_rv32(cpu, ctr_idx);\n- } else {\n- ret = riscv_pmu_incr_ctr_rv64(cpu, ctr_idx);\n- }\n-\n- return ret;\n-}\n-\n-bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,\n- uint32_t target_ctr)\n-{\n- RISCVCPU *cpu;\n- uint32_t event_idx;\n- uint32_t ctr_idx;\n-\n- /* Fixed instret counter */\n- if (target_ctr == 2) {\n- return true;\n- }\n-\n- cpu = env_archcpu(env);\n- if (!cpu->pmu_event_ctr_map) {\n- return false;\n- }\n-\n- event_idx = RISCV_PMU_EVENT_HW_INSTRUCTIONS;\n- ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map,\n- GUINT_TO_POINTER(event_idx)));\n- if (!ctr_idx) {\n- return false;\n- }\n-\n- return target_ctr == ctr_idx ? true : false;\n-}\n-\n-bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr)\n-{\n- RISCVCPU *cpu;\n- uint32_t event_idx;\n- uint32_t ctr_idx;\n-\n- /* Fixed mcycle counter */\n- if (target_ctr == 0) {\n- return true;\n- }\n-\n- cpu = env_archcpu(env);\n- if (!cpu->pmu_event_ctr_map) {\n- return false;\n- }\n-\n- event_idx = RISCV_PMU_EVENT_HW_CPU_CYCLES;\n- ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map,\n- GUINT_TO_POINTER(event_idx)));\n-\n- /* Counter zero is not used for event_ctr_map */\n- if (!ctr_idx) {\n- return false;\n- }\n-\n- return (target_ctr == ctr_idx) ? true : false;\n-}\n-\n-static gboolean pmu_remove_event_map(gpointer key, gpointer value,\n- gpointer udata)\n-{\n- return (GPOINTER_TO_UINT(value) == GPOINTER_TO_UINT(udata)) ? true : false;\n-}\n-\n static int64_t pmu_icount_ticks_to_ns(int64_t value)\n {\n int64_t ret = 0;\n@@ -376,50 +209,6 @@ static int64_t pmu_icount_ticks_to_ns(int64_t value)\n return ret;\n }\n \n-int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,\n- uint32_t ctr_idx)\n-{\n- uint32_t event_idx;\n- RISCVCPU *cpu = env_archcpu(env);\n-\n- if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map) {\n- return -1;\n- }\n-\n- /*\n- * Expected mhpmevent value is zero for reset case. Remove the current\n- * mapping.\n- */\n- if (!(value & MHPMEVENT_IDX_MASK)) {\n- g_hash_table_foreach_remove(cpu->pmu_event_ctr_map,\n- pmu_remove_event_map,\n- GUINT_TO_POINTER(ctr_idx));\n- return 0;\n- }\n-\n- event_idx = value & MHPMEVENT_IDX_MASK;\n- if (g_hash_table_lookup(cpu->pmu_event_ctr_map,\n- GUINT_TO_POINTER(event_idx))) {\n- return 0;\n- }\n-\n- switch (event_idx) {\n- case RISCV_PMU_EVENT_HW_CPU_CYCLES:\n- case RISCV_PMU_EVENT_HW_INSTRUCTIONS:\n- case RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS:\n- case RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS:\n- case RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS:\n- break;\n- default:\n- /* We don't support any raw events right now */\n- return -1;\n- }\n- g_hash_table_insert(cpu->pmu_event_ctr_map, GUINT_TO_POINTER(event_idx),\n- GUINT_TO_POINTER(ctr_idx));\n-\n- return 0;\n-}\n-\n static bool pmu_hpmevent_is_of_set(CPURISCVState *env, uint32_t ctr_idx)\n {\n target_ulong mhpmevent_val;\n@@ -457,23 +246,19 @@ static bool pmu_hpmevent_set_of_if_clear(CPURISCVState *env, uint32_t ctr_idx)\n return false;\n }\n \n-static void pmu_timer_trigger_irq(RISCVCPU *cpu,\n- enum riscv_pmu_event_idx evt_idx)\n+static void pmu_timer_trigger_irq(RISCVCPU *cpu, uint32_t ctr_idx)\n {\n- uint32_t ctr_idx;\n CPURISCVState *env = &cpu->env;\n PMUCTRState *counter;\n int64_t irq_trigger_at;\n uint64_t curr_ctr_val, curr_ctrh_val;\n uint64_t ctr_val;\n \n- if (evt_idx != RISCV_PMU_EVENT_HW_CPU_CYCLES &&\n- evt_idx != RISCV_PMU_EVENT_HW_INSTRUCTIONS) {\n+ if (ctr_idx != HPM_MINSTRET_IDX &&\n+ ctr_idx != HPM_MCYCLE_IDX) {\n return;\n }\n \n- ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map,\n- GUINT_TO_POINTER(evt_idx)));\n if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) {\n return;\n }\n@@ -523,10 +308,13 @@ static void pmu_timer_trigger_irq(RISCVCPU *cpu,\n void riscv_pmu_timer_cb(void *priv)\n {\n RISCVCPU *cpu = priv;\n+ uint32_t ctr_idx;\n \n- /* Timer event was triggered only for these events */\n- pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_CPU_CYCLES);\n- pmu_timer_trigger_irq(cpu, RISCV_PMU_EVENT_HW_INSTRUCTIONS);\n+ for (ctr_idx = 0; ctr_idx < RV_MAX_MHPMCOUNTERS; ctr_idx++) {\n+ if (riscv_pmu_counter_valid(cpu, ctr_idx)) {\n+ pmu_timer_trigger_irq(cpu, ctr_idx);\n+ }\n+ }\n }\n \n int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx)\n@@ -557,8 +345,8 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx)\n overflow_left = overflow_delta - INT64_MAX;\n }\n \n- if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||\n- riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {\n+ if (ctr_idx == HPM_MCYCLE_IDX ||\n+ ctr_idx == HPM_MINSTRET_IDX) {\n overflow_ns = pmu_icount_ticks_to_ns((int64_t)overflow_delta);\n overflow_left = pmu_icount_ticks_to_ns(overflow_left) ;\n } else {\n@@ -592,12 +380,6 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp)\n return;\n }\n \n- cpu->pmu_event_ctr_map = g_hash_table_new(g_direct_hash, g_direct_equal);\n- if (!cpu->pmu_event_ctr_map) {\n- error_setg(errp, \"Unable to allocate PMU event hash table\");\n- return;\n- }\n-\n cpu->pmu_avail_ctrs = cpu->cfg.pmu_mask;\n }\n \ndiff --git a/target/riscv/pmu.h b/target/riscv/pmu.h\nindex 8f019bea9f..97b167d8f2 100644\n--- a/target/riscv/pmu.h\n+++ b/target/riscv/pmu.h\n@@ -22,15 +22,8 @@\n #include \"cpu.h\"\n #include \"qapi/error.h\"\n \n-bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,\n- uint32_t target_ctr);\n-bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env,\n- uint32_t target_ctr);\n void riscv_pmu_timer_cb(void *priv);\n void riscv_pmu_init(RISCVCPU *cpu, Error **errp);\n-int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,\n- uint32_t ctr_idx);\n-int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx);\n void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name);\n int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,\n uint32_t ctr_idx);\n","prefixes":["RFC","3/6"]}