{"id":2175698,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175698/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20251218183122.408690-3-sergeev0xef@gmail.com>","date":"2025-12-18T18:31:17","name":"[RFC,2/6] target/riscv: Reimplement Smcdeleg/Ssccfg via read_*, write_* methods","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"5e1e107b74d20e52d366519544c836ed65d64413","submitter":{"id":92294,"url":"http://patchwork.ozlabs.org/api/1.0/people/92294/?format=json","name":"Aleksandr Sergeev","email":"sergeev0xef@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20251218183122.408690-3-sergeev0xef@gmail.com/mbox/","series":[{"id":485896,"url":"http://patchwork.ozlabs.org/api/1.0/series/485896/?format=json","date":"2025-12-18T18:31:20","name":"More extendable PMU subsystem.","version":1,"mbox":"http://patchwork.ozlabs.org/series/485896/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175698/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=BuLzkFvw;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dXK8D1zj0z1y2F\n\tfor ; Fri, 19 Dec 2025 05:34:36 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1vWIo7-0003x5-NF; Thu, 18 Dec 2025 13:32:59 -0500","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1vWImz-0003mY-3O\n for qemu-devel@nongnu.org; Thu, 18 Dec 2025 13:31:49 -0500","from mail-lf1-x129.google.com ([2a00:1450:4864:20::129])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1vWImx-0007LQ-6E\n for qemu-devel@nongnu.org; Thu, 18 Dec 2025 13:31:48 -0500","by mail-lf1-x129.google.com with SMTP id\n 2adb3069b0e04-59577c4c7c1so1742053e87.1\n for ; Thu, 18 Dec 2025 10:31:46 -0800 (PST)","from NB-8855.Dlink ([81.201.19.27]) by smtp.gmail.com with ESMTPSA\n id\n 2adb3069b0e04-59a185dd229sm46777e87.22.2025.12.18.10.31.44\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 18 Dec 2025 10:31:44 -0800 (PST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20230601; t=1766082705; x=1766687505; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=bvdG33TRWp8WNQPzYXmaerPpkmBvUESr5mSsOVtQ4Q8=;\n b=BuLzkFvwzDkO+rKme4VWoYYghrwHYh0nsrrwPp+YhneQ5Z86FTvg2FI+NYBBfykawS\n tM0gFN5ZIxHzOAMDqPapwbHNvBfr2QYdAhWOEaEc2YPWsIgPal/RQtsZijISpkM7Z//p\n OCt/xziRh4IEx7+MhfM7mysqS7y+TCtzDUqL8silsHtBG40ZW5MEhgtNUheB1BthMQYJ\n GhfNsJ5xAl3szc7EAzZXuHZtoXm2m74mPdEvMMCxpSdmGQm/zOism+tNZ3Y5dWuU9LIX\n dm26OmL7eO+/XrDeTxwfhaAcFazGbSRsqmySqmgBLep0hBEsSKH+Xo3EkY41UmqSDmsa\n F63A==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1766082705; x=1766687505;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=bvdG33TRWp8WNQPzYXmaerPpkmBvUESr5mSsOVtQ4Q8=;\n b=pDC0huw1ssAvHwGEYNKZe/XT38y0tCNsamM6+gjbQMVPVyHZMbCd7bNKndoDSCRV+S\n bJv8KIO/U35vDjMJJaKBXZoZ6w2bLpBbaYNUly6Yn8ePIZCpEjNuqwFStAbET/4qric/\n RnNhlC50JW+5nTeD3QjDrjzma90KVzIx5KF6icGSF54eqKADCDxqmfeOFEo6gMcb0d9H\n et7R6y5kmEN9OSZkUtJ2yfz8l6Iuc51iSTlwu6wY/uGANceUKVKZY1ZuI2jXR8ew+hjm\n FcBZF4XZHDmTF8WZU4aXPUMY0dBwLekgqVqZopXd1eirWX7bYtXi9lzB2NaUisT8v9Sn\n kkwA==","X-Gm-Message-State":"AOJu0Yx75gtKqsKK6S20070LlYowoR6SqHF64RsT7npEyfhyBO7J6z8t\n bFOnbJ125MeOE58pq4CkWFvAQcmBg22RmuHYKGITFSFAY62r/K4DM4jFD/uLaf9z","X-Gm-Gg":"AY/fxX6uY8zCMT8xviYrT3AW3Lyy8lLMLI7X8E+Ya2Re1Oy4Y8m5rpFpCmtDEKhxc/X\n MTkTwKSO8tIgjkD758WUMIIcLZcTR3POFmD0wLdpqIwfUxFHauwi+MukKYBzp/X4pAR22c5HJ/P\n i6e9yeO1S1r4LajGApZhVeoSiC/Qhxmg81ZUva2opce/7MVCvwbH66KrqBz6kikmhsY+026jhJL\n aUyEO0yUtctp83cr4DCkbgVVGHGco8dTFjyL2G/ytJfe1O868IbfdburDGFvJT5pmTkukC9mcuX\n E2AipUhZDpRy6rdIwvM3fA+mdHPAgJNzIYTx4JUOg/m03RgHPP2+OzWj15EQKvycJF42L9ZJFHY\n 0GuGkUcNY99kXUioP43TDZ76FrWe5RHuQu63rEIc7aoGukhubbXXh5kEitHOidwAdlmOeBMsu4k\n KBqUM22Aht36PL","X-Google-Smtp-Source":"\n AGHT+IEBB/Rsoe4o74O4RaCcS/gINOdKEL5eskNgr6M0dfB3klPawtUMVkEz7op//XGHFJr55NW45g==","X-Received":"by 2002:a05:6512:3d9e:b0:595:7d7c:59a9 with SMTP id\n 2adb3069b0e04-59a17d6bb20mr161845e87.22.1766082704953;\n Thu, 18 Dec 2025 10:31:44 -0800 (PST)","From":"Aleksandr Sergeev ","To":"qemu-devel@nongnu.org","Cc":"halip0503@gmail.com,\n\tAleksandr Sergeev ","Subject":"[RFC PATCH 2/6] target/riscv: Reimplement Smcdeleg/Ssccfg via read_*,\n write_* methods","Date":"Thu, 18 Dec 2025 21:31:17 +0300","Message-ID":"<20251218183122.408690-3-sergeev0xef@gmail.com>","X-Mailer":"git-send-email 2.51.0","In-Reply-To":"<20251218183122.408690-1-sergeev0xef@gmail.com>","References":"<20251218183122.408690-1-sergeev0xef@gmail.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::129;\n envelope-from=sergeev0xef@gmail.com; helo=mail-lf1-x129.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-Mailman-Approved-At":"Thu, 18 Dec 2025 13:32:41 -0500","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Methods rmw_cd_mhpmcounter(), rmw_cd_mhpmcounterh(),\nrmw_cd_mhpmevent(), rmw_cd_mhpmeventh(), rmw_cd_ctr_cfg(),\nrmw_cd_ctr_cfgh() contain the same code as read_hmpcounter(),\nwrite_mhpmcounter(), etc. To avoid the same logic\nbeing implemented twice, lets re-call methods from one another.\n\nSigned-off-by: Aleksandr Sergeev \nReviewed-by: Alexei Filippov \n---\n target/riscv/csr.c | 80 +++++++++++++---------------------------------\n 1 file changed, 22 insertions(+), 58 deletions(-)","diff":"diff --git a/target/riscv/csr.c b/target/riscv/csr.c\nindex 8bdbc71160..81475ec9a3 100644\n--- a/target/riscv/csr.c\n+++ b/target/riscv/csr.c\n@@ -1419,9 +1419,9 @@ static int rmw_cd_mhpmcounter(CPURISCVState *env, int ctr_idx,\n }\n \n if (!wr_mask && val) {\n- riscv_pmu_read_ctr(env, val, false, ctr_idx);\n+ read_hpmcounter(env, CSR_MCYCLE + ctr_idx, val);\n } else if (wr_mask) {\n- riscv_pmu_write_ctr(env, new_val, ctr_idx);\n+ write_mhpmcounter(env, CSR_MCYCLE + ctr_idx, new_val, 0);\n } else {\n return -EINVAL;\n }\n@@ -1438,9 +1438,9 @@ static int rmw_cd_mhpmcounterh(CPURISCVState *env, int ctr_idx,\n }\n \n if (!wr_mask && val) {\n- riscv_pmu_read_ctr(env, val, true, ctr_idx);\n+ read_hpmcounterh(env, CSR_MCYCLEH + ctr_idx, val);\n } else if (wr_mask) {\n- riscv_pmu_write_ctrh(env, new_val, ctr_idx);\n+ write_mhpmcounterh(env, CSR_MCYCLEH + ctr_idx, new_val, 0);\n } else {\n return -EINVAL;\n }\n@@ -1448,31 +1448,18 @@ static int rmw_cd_mhpmcounterh(CPURISCVState *env, int ctr_idx,\n return 0;\n }\n \n-static int rmw_cd_mhpmevent(CPURISCVState *env, int evt_index,\n+static int rmw_cd_mhpmevent(CPURISCVState *env, int ctr_idx,\n target_ulong *val, target_ulong new_val,\n target_ulong wr_mask)\n {\n- uint64_t mhpmevt_val = new_val;\n-\n if (wr_mask != 0 && wr_mask != -1) {\n return -EINVAL;\n }\n \n if (!wr_mask && val) {\n- *val = env->mhpmevent_val[evt_index];\n- if (riscv_cpu_cfg(env)->ext_sscofpmf) {\n- *val &= ~MHPMEVENT_BIT_MINH;\n- }\n+ read_mhpmevent(env, ctr_idx - 3 + CSR_MHPMEVENT3, val);\n } else if (wr_mask) {\n- wr_mask &= ~MHPMEVENT_BIT_MINH;\n- mhpmevt_val = (new_val & wr_mask) |\n- (env->mhpmevent_val[evt_index] & ~wr_mask);\n- if (riscv_cpu_mxl(env) == MXL_RV32) {\n- mhpmevt_val = mhpmevt_val |\n- ((uint64_t)env->mhpmeventh_val[evt_index] << 32);\n- }\n- env->mhpmevent_val[evt_index] = mhpmevt_val;\n- riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);\n+ write_mhpmevent(env, ctr_idx - 3 + CSR_MHPMEVENT3, new_val, 0);\n } else {\n return -EINVAL;\n }\n@@ -1480,29 +1467,18 @@ static int rmw_cd_mhpmevent(CPURISCVState *env, int evt_index,\n return 0;\n }\n \n-static int rmw_cd_mhpmeventh(CPURISCVState *env, int evt_index,\n+static int rmw_cd_mhpmeventh(CPURISCVState *env, int ctr_idx,\n target_ulong *val, target_ulong new_val,\n target_ulong wr_mask)\n {\n- uint64_t mhpmevth_val;\n- uint64_t mhpmevt_val = env->mhpmevent_val[evt_index];\n-\n if (wr_mask != 0 && wr_mask != -1) {\n return -EINVAL;\n }\n \n if (!wr_mask && val) {\n- *val = env->mhpmeventh_val[evt_index];\n- if (riscv_cpu_cfg(env)->ext_sscofpmf) {\n- *val &= ~MHPMEVENTH_BIT_MINH;\n- }\n+ read_mhpmeventh(env, ctr_idx - 3 + CSR_MHPMEVENT3H, val);\n } else if (wr_mask) {\n- wr_mask &= ~MHPMEVENTH_BIT_MINH;\n- env->mhpmeventh_val[evt_index] =\n- (new_val & wr_mask) | (env->mhpmeventh_val[evt_index] & ~wr_mask);\n- mhpmevth_val = env->mhpmeventh_val[evt_index];\n- mhpmevt_val = mhpmevt_val | (mhpmevth_val << 32);\n- riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);\n+ write_mhpmeventh(env, ctr_idx - 3 + CSR_MHPMEVENT3H, new_val, 0);\n } else {\n return -EINVAL;\n }\n@@ -1514,21 +1490,18 @@ static int rmw_cd_ctr_cfg(CPURISCVState *env, int cfg_index, target_ulong *val,\n target_ulong new_val, target_ulong wr_mask)\n {\n switch (cfg_index) {\n- case 0: /* CYCLECFG */\n+ case HPM_MCYCLE_IDX:\n if (wr_mask) {\n- wr_mask &= ~MCYCLECFG_BIT_MINH;\n- env->mcyclecfg = (new_val & wr_mask) | (env->mcyclecfg & ~wr_mask);\n+ write_mcyclecfg(env, CSR_MCYCLE, new_val, 0);\n } else {\n- *val = env->mcyclecfg &= ~MHPMEVENTH_BIT_MINH;\n+ read_mcyclecfg(env, CSR_MCYCLE, val);\n }\n break;\n- case 2: /* INSTRETCFG */\n+ case HPM_MINSTRET_IDX:\n if (wr_mask) {\n- wr_mask &= ~MINSTRETCFG_BIT_MINH;\n- env->minstretcfg = (new_val & wr_mask) |\n- (env->minstretcfg & ~wr_mask);\n+ write_minstretcfg(env, CSR_MINSTRET, new_val, 0);\n } else {\n- *val = env->minstretcfg &= ~MHPMEVENTH_BIT_MINH;\n+ read_minstretcfg(env, CSR_MINSTRET, val);\n }\n break;\n default:\n@@ -1540,28 +1513,19 @@ static int rmw_cd_ctr_cfg(CPURISCVState *env, int cfg_index, target_ulong *val,\n static int rmw_cd_ctr_cfgh(CPURISCVState *env, int cfg_index, target_ulong *val,\n target_ulong new_val, target_ulong wr_mask)\n {\n-\n- if (riscv_cpu_mxl(env) != MXL_RV32) {\n- return RISCV_EXCP_ILLEGAL_INST;\n- }\n-\n switch (cfg_index) {\n- case 0: /* CYCLECFGH */\n+ case HPM_MCYCLE_IDX:\n if (wr_mask) {\n- wr_mask &= ~MCYCLECFGH_BIT_MINH;\n- env->mcyclecfgh = (new_val & wr_mask) |\n- (env->mcyclecfgh & ~wr_mask);\n+ write_mcyclecfgh(env, CSR_MCYCLEH, new_val, 0);\n } else {\n- *val = env->mcyclecfgh;\n+ read_mcyclecfgh(env, CSR_MCYCLEH, val);\n }\n break;\n- case 2: /* INSTRETCFGH */\n+ case HPM_MINSTRET_IDX:\n if (wr_mask) {\n- wr_mask &= ~MINSTRETCFGH_BIT_MINH;\n- env->minstretcfgh = (new_val & wr_mask) |\n- (env->minstretcfgh & ~wr_mask);\n+ write_minstretcfgh(env, CSR_MINSTRETH, new_val, 0);\n } else {\n- *val = env->minstretcfgh;\n+ read_minstretcfgh(env, CSR_MINSTRETH, val);\n }\n break;\n default:\n","prefixes":["RFC","2/6"]}