{"id":2175697,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175697/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20251218183122.408690-2-sergeev0xef@gmail.com>","date":"2025-12-18T18:31:16","name":"[RFC,1/6] target/riscv: Refactor counter index calculation.","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"fbf8e2eac842f2faedd5e4478634be45ce4fb3e7","submitter":{"id":92294,"url":"http://patchwork.ozlabs.org/api/1.0/people/92294/?format=json","name":"Aleksandr Sergeev","email":"sergeev0xef@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20251218183122.408690-2-sergeev0xef@gmail.com/mbox/","series":[{"id":485896,"url":"http://patchwork.ozlabs.org/api/1.0/series/485896/?format=json","date":"2025-12-18T18:31:20","name":"More extendable PMU subsystem.","version":1,"mbox":"http://patchwork.ozlabs.org/series/485896/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175697/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=frfUp7Cz;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-lf1-x132.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-Mailman-Approved-At":"Thu, 18 Dec 2025 13:32:34 -0500","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"When working with hpm registers, we need to calculate counter index\nby csr number. By now it was done manually. Let's add a function --\nriscv_pmu_csrno_to_ctr_idx(), which incapsulates this action.\n\nSigned-off-by: Aleksandr Sergeev \nReviewed-by: Alexei Filippov \n---\n target/riscv/cpu_bits.h | 4 +++\n target/riscv/csr.c | 73 ++++++++++++++---------------------------\n target/riscv/pmu.c | 44 +++++++++++++++++++++++++\n target/riscv/pmu.h | 1 +\n 4 files changed, 73 insertions(+), 49 deletions(-)","diff":"diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h\nindex b62dd82fe7..5c3c1af64e 100644\n--- a/target/riscv/cpu_bits.h\n+++ b/target/riscv/cpu_bits.h\n@@ -1145,6 +1145,10 @@ typedef enum CTRType {\n /* RISC-V-specific interrupt pending bits. */\n #define CPU_INTERRUPT_RNMI CPU_INTERRUPT_TGT_EXT_0\n \n+#define HPM_MCYCLE_IDX 0\n+#define HPM_MTIME_IDX 1\n+#define HPM_MINSTRET_IDX 2\n+\n /* JVT CSR bits */\n #define JVT_MODE 0x3F\n #define JVT_BASE (~0x3F)\ndiff --git a/target/riscv/csr.c b/target/riscv/csr.c\nindex 5c91658c3d..8bdbc71160 100644\n--- a/target/riscv/csr.c\n+++ b/target/riscv/csr.c\n@@ -110,17 +110,8 @@ static RISCVException ctr(CPURISCVState *env, int csrno)\n {\n #if !defined(CONFIG_USER_ONLY)\n RISCVCPU *cpu = env_archcpu(env);\n- int ctr_index;\n- target_ulong ctr_mask;\n- int base_csrno = CSR_CYCLE;\n- bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false;\n-\n- if (rv32 && csrno >= CSR_CYCLEH) {\n- /* Offset for RV32 hpmcounternh counters */\n- base_csrno += 0x80;\n- }\n- ctr_index = csrno - base_csrno;\n- ctr_mask = BIT(ctr_index);\n+ uint32_t ctr_index = riscv_pmu_csrno_to_ctr_idx(csrno);\n+ target_ulong ctr_mask = BIT(ctr_index);\n \n if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) ||\n (csrno >= CSR_CYCLEH && csrno <= CSR_INSTRETH)) {\n@@ -1166,9 +1157,9 @@ static RISCVException write_minstretcfgh(CPURISCVState *env, int csrno,\n static RISCVException read_mhpmevent(CPURISCVState *env, int csrno,\n target_ulong *val)\n {\n- int evt_index = csrno - CSR_MCOUNTINHIBIT;\n+ uint32_t ctr_idx = riscv_pmu_csrno_to_ctr_idx(csrno);\n \n- *val = env->mhpmevent_val[evt_index];\n+ *val = env->mhpmevent_val[ctr_idx];\n \n return RISCV_EXCP_NONE;\n }\n@@ -1176,14 +1167,15 @@ static RISCVException read_mhpmevent(CPURISCVState *env, int csrno,\n static RISCVException write_mhpmevent(CPURISCVState *env, int csrno,\n target_ulong val, uintptr_t ra)\n {\n- int evt_index = csrno - CSR_MCOUNTINHIBIT;\n+ uint32_t ctr_idx = riscv_pmu_csrno_to_ctr_idx(csrno);\n+\n uint64_t mhpmevt_val = val;\n uint64_t inh_avail_mask;\n \n if (riscv_cpu_mxl(env) == MXL_RV32) {\n- env->mhpmevent_val[evt_index] = val;\n+ env->mhpmevent_val[ctr_idx] = val;\n mhpmevt_val = mhpmevt_val |\n- ((uint64_t)env->mhpmeventh_val[evt_index] << 32);\n+ ((uint64_t)env->mhpmeventh_val[ctr_idx] << 32);\n } else {\n inh_avail_mask = ~MHPMEVENT_FILTER_MASK | MHPMEVENT_BIT_MINH;\n inh_avail_mask |= riscv_has_ext(env, RVU) ? MHPMEVENT_BIT_UINH : 0;\n@@ -1193,10 +1185,10 @@ static RISCVException write_mhpmevent(CPURISCVState *env, int csrno,\n inh_avail_mask |= (riscv_has_ext(env, RVH) &&\n riscv_has_ext(env, RVS)) ? MHPMEVENT_BIT_VSINH : 0;\n mhpmevt_val = val & inh_avail_mask;\n- env->mhpmevent_val[evt_index] = mhpmevt_val;\n+ env->mhpmevent_val[ctr_idx] = mhpmevt_val;\n }\n \n- riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);\n+ riscv_pmu_update_event_map(env, mhpmevt_val, ctr_idx);\n \n return RISCV_EXCP_NONE;\n }\n@@ -1204,9 +1196,9 @@ static RISCVException write_mhpmevent(CPURISCVState *env, int csrno,\n static RISCVException read_mhpmeventh(CPURISCVState *env, int csrno,\n target_ulong *val)\n {\n- int evt_index = csrno - CSR_MHPMEVENT3H + 3;\n+ uint32_t ctr_idx = riscv_pmu_csrno_to_ctr_idx(csrno);\n \n- *val = env->mhpmeventh_val[evt_index];\n+ *val = env->mhpmeventh_val[ctr_idx];\n \n return RISCV_EXCP_NONE;\n }\n@@ -1214,9 +1206,9 @@ static RISCVException read_mhpmeventh(CPURISCVState *env, int csrno,\n static RISCVException write_mhpmeventh(CPURISCVState *env, int csrno,\n target_ulong val, uintptr_t ra)\n {\n- int evt_index = csrno - CSR_MHPMEVENT3H + 3;\n+ uint32_t ctr_idx = riscv_pmu_csrno_to_ctr_idx(csrno);\n uint64_t mhpmevth_val;\n- uint64_t mhpmevt_val = env->mhpmevent_val[evt_index];\n+ uint64_t mhpmevt_val = env->mhpmevent_val[ctr_idx];\n target_ulong inh_avail_mask = (target_ulong)(~MHPMEVENTH_FILTER_MASK |\n MHPMEVENTH_BIT_MINH);\n \n@@ -1229,9 +1221,9 @@ static RISCVException write_mhpmeventh(CPURISCVState *env, int csrno,\n \n mhpmevth_val = val & inh_avail_mask;\n mhpmevt_val = mhpmevt_val | (mhpmevth_val << 32);\n- env->mhpmeventh_val[evt_index] = mhpmevth_val;\n+ env->mhpmeventh_val[ctr_idx] = mhpmevth_val;\n \n- riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);\n+ riscv_pmu_update_event_map(env, mhpmevt_val, ctr_idx);\n \n return RISCV_EXCP_NONE;\n }\n@@ -1357,7 +1349,7 @@ static RISCVException riscv_pmu_write_ctrh(CPURISCVState *env, target_ulong val,\n static RISCVException write_mhpmcounter(CPURISCVState *env, int csrno,\n target_ulong val, uintptr_t ra)\n {\n- int ctr_idx = csrno - CSR_MCYCLE;\n+ uint32_t ctr_idx = riscv_pmu_csrno_to_ctr_idx(csrno);\n \n return riscv_pmu_write_ctr(env, val, ctr_idx);\n }\n@@ -1365,7 +1357,7 @@ static RISCVException write_mhpmcounter(CPURISCVState *env, int csrno,\n static RISCVException write_mhpmcounterh(CPURISCVState *env, int csrno,\n target_ulong val, uintptr_t ra)\n {\n- int ctr_idx = csrno - CSR_MCYCLEH;\n+ uint32_t ctr_idx = riscv_pmu_csrno_to_ctr_idx(csrno);\n \n return riscv_pmu_write_ctrh(env, val, ctr_idx);\n }\n@@ -1406,33 +1398,16 @@ RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,\n static RISCVException read_hpmcounter(CPURISCVState *env, int csrno,\n target_ulong *val)\n {\n- uint16_t ctr_index;\n-\n- if (csrno >= CSR_MCYCLE && csrno <= CSR_MHPMCOUNTER31) {\n- ctr_index = csrno - CSR_MCYCLE;\n- } else if (csrno >= CSR_CYCLE && csrno <= CSR_HPMCOUNTER31) {\n- ctr_index = csrno - CSR_CYCLE;\n- } else {\n- return RISCV_EXCP_ILLEGAL_INST;\n- }\n-\n- return riscv_pmu_read_ctr(env, val, false, ctr_index);\n+ uint32_t ctr_idx = riscv_pmu_csrno_to_ctr_idx(csrno);\n+ return riscv_pmu_read_ctr(env, val, false, ctr_idx);\n }\n \n static RISCVException read_hpmcounterh(CPURISCVState *env, int csrno,\n target_ulong *val)\n {\n- uint16_t ctr_index;\n \n- if (csrno >= CSR_MCYCLEH && csrno <= CSR_MHPMCOUNTER31H) {\n- ctr_index = csrno - CSR_MCYCLEH;\n- } else if (csrno >= CSR_CYCLEH && csrno <= CSR_HPMCOUNTER31H) {\n- ctr_index = csrno - CSR_CYCLEH;\n- } else {\n- return RISCV_EXCP_ILLEGAL_INST;\n- }\n-\n- return riscv_pmu_read_ctr(env, val, true, ctr_index);\n+ uint32_t ctr_idx = riscv_pmu_csrno_to_ctr_idx(csrno);\n+ return riscv_pmu_read_ctr(env, val, true, ctr_idx);\n }\n \n static int rmw_cd_mhpmcounter(CPURISCVState *env, int ctr_idx,\n@@ -1599,8 +1574,8 @@ static int rmw_cd_ctr_cfgh(CPURISCVState *env, int cfg_index, target_ulong *val,\n static RISCVException read_scountovf(CPURISCVState *env, int csrno,\n target_ulong *val)\n {\n- int mhpmevt_start = CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT;\n- int i;\n+ uint32_t mhpmevt_start = riscv_pmu_csrno_to_ctr_idx(CSR_MHPMEVENT3);\n+ uint32_t i;\n *val = 0;\n target_ulong *mhpm_evt_val;\n uint64_t of_bit_mask;\ndiff --git a/target/riscv/pmu.c b/target/riscv/pmu.c\nindex a68809eef3..b983eadd83 100644\n--- a/target/riscv/pmu.c\n+++ b/target/riscv/pmu.c\n@@ -600,3 +600,47 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp)\n \n cpu->pmu_avail_ctrs = cpu->cfg.pmu_mask;\n }\n+\n+uint32_t riscv_pmu_csrno_to_ctr_idx(int csrno)\n+{\n+ #define CASE_RANGE(low, high, offset) { \\\n+ case (low)...(high): \\\n+ return csrno - (low) + (offset); \\\n+ }\n+ #define HPMCOUNTER_START (HPM_MINSTRET_IDX + 1)\n+\n+ switch (csrno) {\n+ CASE_RANGE(CSR_MHPMEVENT3, CSR_MHPMEVENT31, HPMCOUNTER_START)\n+ CASE_RANGE(CSR_MHPMEVENT3H, CSR_MHPMEVENT31H, HPMCOUNTER_START)\n+ CASE_RANGE(CSR_HPMCOUNTER3, CSR_HPMCOUNTER31, HPMCOUNTER_START)\n+ CASE_RANGE(CSR_HPMCOUNTER3H, CSR_HPMCOUNTER31H, HPMCOUNTER_START)\n+ CASE_RANGE(CSR_MHPMCOUNTER3, CSR_MHPMCOUNTER31, HPMCOUNTER_START)\n+ CASE_RANGE(CSR_MHPMCOUNTER3H, CSR_MHPMCOUNTER31H, HPMCOUNTER_START)\n+\n+ case CSR_MCYCLE:\n+ case CSR_MCYCLEH:\n+ case CSR_CYCLE:\n+ case CSR_CYCLEH:\n+ case CSR_MCYCLECFG:\n+ case CSR_MCYCLECFGH:\n+ return HPM_MCYCLE_IDX;\n+\n+ case CSR_MINSTRET:\n+ case CSR_MINSTRETH:\n+ case CSR_INSTRET:\n+ case CSR_INSTRETH:\n+ case CSR_MINSTRETCFG:\n+ case CSR_MINSTRETCFGH:\n+ return HPM_MINSTRET_IDX;\n+\n+ case CSR_TIME:\n+ case CSR_TIMEH:\n+ return HPM_MTIME_IDX;\n+\n+ default:\n+ g_assert_not_reached();\n+ }\n+\n+ #undef HPMCOUNTER_START\n+ #undef CASE_RANGE\n+}\ndiff --git a/target/riscv/pmu.h b/target/riscv/pmu.h\nindex 3853d0e262..8f019bea9f 100644\n--- a/target/riscv/pmu.h\n+++ b/target/riscv/pmu.h\n@@ -38,5 +38,6 @@ void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv,\n bool new_virt);\n RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,\n bool upper_half, uint32_t ctr_idx);\n+uint32_t riscv_pmu_csrno_to_ctr_idx(int csrno);\n \n #endif /* RISCV_PMU_H */\n","prefixes":["RFC","1/6"]}