{"id":2175686,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175686/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20251218181812.58363-3-philmd@linaro.org>","date":"2025-12-18T18:18:07","name":"[2/6] hw/net/opencores: Clarify MMIO read/write handlers expect 32-bit access","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1b50843109cc676e890ee15dabdc9d1743347bff","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/1.0/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20251218181812.58363-3-philmd@linaro.org/mbox/","series":[{"id":485895,"url":"http://patchwork.ozlabs.org/api/1.0/series/485895/?format=json","date":"2025-12-18T18:18:07","name":"hw: Preparatory cleanups previous to remove DEVICE_NATIVE_ENDIAN","version":1,"mbox":"http://patchwork.ozlabs.org/series/485895/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175686/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=FBhttFlh;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Tsirkin\" , Max Filippov ,\n qemu-arm@nongnu.org, Manos Pitsidianakis ,\n qemu-rust@nongnu.org,\n =?utf-8?q?Marc-Andr=C3=A9_Lureau?= ,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","Subject":"[PATCH 2/6] hw/net/opencores: Clarify MMIO read/write handlers expect\n 32-bit access","Date":"Thu, 18 Dec 2025 19:18:07 +0100","Message-ID":"<20251218181812.58363-3-philmd@linaro.org>","X-Mailer":"git-send-email 2.52.0","In-Reply-To":"<20251218181812.58363-1-philmd@linaro.org>","References":"<20251218181812.58363-1-philmd@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::442;\n envelope-from=philmd@linaro.org; helo=mail-wr1-x442.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"The read/write handlers access array of 32-bit register by index:\n\n 277 struct OpenEthState {\n ..\n 287 uint32_t regs[REG_MAX];\n ..\n 291 };\n\n 546 static uint64_t open_eth_reg_read(void *opaque,\n 547 hwaddr addr, unsigned int size)\n 548 {\n ..\n 551 OpenEthState *s = opaque;\n 552 unsigned idx = addr / 4;\n ..\n 559 v = s->regs[idx];\n ..\n 563 return v;\n 564 }\n\nThis is a 32-bit implementation. Make that explicit in the\nMemoryRegionOps structure (this doesn't change the maximum\naccess size, which -- being unset -- is 64-bit).\n\nMove the structure just after the handlers to ease code review.\n\nSigned-off-by: Philippe Mathieu-Daudé \n---\n hw/net/opencores_eth.c | 15 +++++++++------\n 1 file changed, 9 insertions(+), 6 deletions(-)","diff":"diff --git a/hw/net/opencores_eth.c b/hw/net/opencores_eth.c\nindex 7e955c01322..bc4565a9a49 100644\n--- a/hw/net/opencores_eth.c\n+++ b/hw/net/opencores_eth.c\n@@ -682,6 +682,15 @@ static void open_eth_reg_write(void *opaque,\n }\n }\n \n+static const MemoryRegionOps open_eth_reg_ops = {\n+ .read = open_eth_reg_read,\n+ .write = open_eth_reg_write,\n+ .impl = {\n+ .min_access_size = 4,\n+ .max_access_size = 4,\n+ },\n+};\n+\n static uint64_t open_eth_desc_read(void *opaque,\n hwaddr addr, unsigned int size)\n {\n@@ -705,12 +714,6 @@ static void open_eth_desc_write(void *opaque,\n open_eth_check_start_xmit(s);\n }\n \n-\n-static const MemoryRegionOps open_eth_reg_ops = {\n- .read = open_eth_reg_read,\n- .write = open_eth_reg_write,\n-};\n-\n static const MemoryRegionOps open_eth_desc_ops = {\n .read = open_eth_desc_read,\n .write = open_eth_desc_write,\n","prefixes":["2/6"]}