{"id":2175663,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175663/?format=json","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.0/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20251218-clk-mtk-improvements-v1-4-72db131ba148@baylibre.com>","date":"2025-12-18T17:17:02","name":"[4/8] clk: mediatek: organize infrasys functions","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"f5bb1286d97fcdb8772338213b8ed6bdbb938e6c","submitter":{"id":87228,"url":"http://patchwork.ozlabs.org/api/1.0/people/87228/?format=json","name":"David Lechner","email":"dlechner@baylibre.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/1.0/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20251218-clk-mtk-improvements-v1-4-72db131ba148@baylibre.com/mbox/","series":[{"id":485889,"url":"http://patchwork.ozlabs.org/api/1.0/series/485889/?format=json","date":"2025-12-18T17:16:58","name":"clk: mediatek: implement of_xlate and dump","version":1,"mbox":"http://patchwork.ozlabs.org/series/485889/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175663/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=MDSI696y;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20251218-clk-mtk-improvements-v1-4-72db131ba148@baylibre.com>","References":"<20251218-clk-mtk-improvements-v1-0-72db131ba148@baylibre.com>","In-Reply-To":"<20251218-clk-mtk-improvements-v1-0-72db131ba148@baylibre.com>","To":"Lukasz Majewski , Ryder Lee ,\n Weijie Gao ,\n Chunfeng Yun ,\n Igor Belwon ,\n GSS_MTK_Uboot_upstream ,\n Tom Rini ","Cc":"Julien Stephan , u-boot@lists.denx.de,\n David Lechner ","X-Mailer":"b4 0.14.3","X-Developer-Signature":"v=1; a=openpgp-sha256; l=9172; i=dlechner@baylibre.com;\n h=from:subject:message-id;\n bh=TYRtyRMhClQZdqEY+bMNXpL6cr8A1jJOedj+qplCJ40=;\n b=owEBhAF7/pANAwAKAcLMIAH/AY/AAcsmYgBpRDcpLyqCg62VGWD0Qiq5lY9uvaHYy341900/G\n fuKDZ3gwxqJAUoEAAEKADQWIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaUQ3KRYcZGxlY2huZXJA\n YmF5bGlicmUuY29tAAoJEMLMIAH/AY/ACaUH/i3t73n2Nj27jot8Q0f82Rh+L54CI3ifZ7BVgpt\n e8AX+MD8PqPYcIdFhMI0BxstgzI9JEanauUjXWBSy5HQtttiXliot71nIV9L+LaqqvFGuoKJlvE\n LJ7eTpEykNXhYBOW1OYCWSdhWhxawoIzhT3kqNT/kLpY5hrRaTlUbK3ALxW1ypvQAGhAZzbshl6\n xJjEjjl+aOploGvwlOwRESSiqORzfUhUiz50ej/rzq3u/R/taZNpqlGzofK+S71+A8P4MFHKbST\n IJmOMaZ1YZGOZzSsDmvP3GGkcDwCdIeByuGCfB6D0TahdbzeAswFgmfo9wD7Yh49ZHR0R58DdIk\n DxY8=","X-Developer-Key":"i=dlechner@baylibre.com; a=openpgp;\n fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03","X-Mailman-Approved-At":"Thu, 18 Dec 2025 18:18:40 +0100","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Move all infrasys ops and related functions next to each other in the\nfile for better organization.\n\nGenerally all ops functions are grouped together like this for the other\nops types (apmixedsys, topckgen, etc). However the infrasys functions\nwere mixed in with the other sections making them harder to find. This\nwill also give a logical place to add any future infrasys-specific\nfunctions.\n\nSigned-off-by: David Lechner \n---\nNote: the diff looks a bit strange because some functions were quite\nsimilar, but this is just cut and paste reordering of 5 functions\nwithout changing any code.\n---\n drivers/clk/mediatek/clk-mtk.c | 200 +++++++++++++++++++++--------------------\n 1 file changed, 101 insertions(+), 99 deletions(-)","diff":"diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c\nindex ffaecbfd306..6ed0f23f685 100644\n--- a/drivers/clk/mediatek/clk-mtk.c\n+++ b/drivers/clk/mediatek/clk-mtk.c\n@@ -424,27 +424,6 @@ static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)\n \treturn mtk_factor_recalc_rate(fdiv, rate);\n }\n \n-static ulong mtk_infrasys_get_factor_rate(struct clk *clk, u32 off)\n-{\n-\tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n-\tconst struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off];\n-\tulong rate;\n-\n-\tswitch (fdiv->flags & CLK_PARENT_MASK) {\n-\tcase CLK_PARENT_TOPCKGEN:\n-\t\trate = mtk_clk_find_parent_rate(clk, fdiv->parent,\n-\t\t\t\t\t\tpriv->parent);\n-\t\tbreak;\n-\tcase CLK_PARENT_XTAL:\n-\t\trate = priv->tree->xtal_rate;\n-\t\tbreak;\n-\tdefault:\n-\t\trate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);\n-\t}\n-\n-\treturn mtk_factor_recalc_rate(fdiv, rate);\n-}\n-\n static ulong mtk_topckgen_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk,\n \t\t\t\t\t const int parent, u16 flags)\n {\n@@ -504,33 +483,6 @@ static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk,\n \t}\n }\n \n-static ulong mtk_infrasys_get_mux_rate(struct clk *clk, u32 off)\n-{\n-\tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n-\tconst struct mtk_composite *mux = &priv->tree->muxes[off];\n-\tu32 index;\n-\n-\tindex = readl(priv->base + mux->mux_reg);\n-\tindex &= mux->mux_mask << mux->mux_shift;\n-\tindex = index >> mux->mux_shift;\n-\n-\t/*\n-\t * Parents can be either from TOPCKGEN or INFRACFG,\n-\t * inspect the mtk_parent struct to check the source\n-\t */\n-\tif (mux->flags & CLK_PARENT_MIXED) {\n-\t\tconst struct mtk_parent *parent = &mux->parent_flags[index];\n-\n-\t\treturn mtk_find_parent_rate(priv, clk, parent->id, parent->flags);\n-\t}\n-\n-\tif (mux->parent[index] == CLK_XTAL &&\n-\t !(priv->tree->flags & CLK_BYPASS_XTAL))\n-\t\treturn priv->tree->xtal_rate;\n-\n-\treturn mtk_find_parent_rate(priv, clk, mux->parent[index], mux->flags);\n-}\n-\n static ulong mtk_topckgen_get_rate(struct clk *clk)\n {\n \tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n@@ -546,42 +498,6 @@ static ulong mtk_topckgen_get_rate(struct clk *clk)\n \t\t\t\t\t\t priv->tree->muxes_offs);\n }\n \n-static ulong mtk_infrasys_get_rate(struct clk *clk)\n-{\n-\tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n-\tint id = mtk_clk_get_id(clk);\n-\tulong rate;\n-\n-\tif (id < priv->tree->fdivs_offs) {\n-\t\trate = priv->tree->fclks[id].rate;\n-\t} else if (id < priv->tree->muxes_offs) {\n-\t\trate = mtk_infrasys_get_factor_rate(clk, id -\n-\t\t\t\t\t\t priv->tree->fdivs_offs);\n-\t/* No gates defined or ID is a MUX */\n-\t} else if (!priv->tree->gates || id < priv->tree->gates_offs) {\n-\t\trate = mtk_infrasys_get_mux_rate(clk, id -\n-\t\t\t\t\t\t priv->tree->muxes_offs);\n-\t/* Only valid with muxes + gates implementation */\n-\t} else {\n-\t\tstruct udevice *parent = NULL;\n-\t\tconst struct mtk_gate *gate;\n-\n-\t\tgate = &priv->tree->gates[id - priv->tree->gates_offs];\n-\t\tif (gate->flags & CLK_PARENT_TOPCKGEN)\n-\t\t\tparent = priv->parent;\n-\t\t/*\n-\t\t * Assume xtal_rate to be declared if some gates have\n-\t\t * XTAL as parent\n-\t\t */\n-\t\telse if (gate->flags & CLK_PARENT_XTAL)\n-\t\t\treturn priv->tree->xtal_rate;\n-\n-\t\trate = mtk_clk_find_parent_rate(clk, gate->parent, parent);\n-\t}\n-\n-\treturn rate;\n-}\n-\n static int mtk_clk_mux_enable(struct clk *clk)\n {\n \tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n@@ -661,22 +577,23 @@ static int mtk_common_clk_set_parent(struct clk *clk, struct clk *parent)\n \t\t\t&priv->tree->muxes[id - priv->tree->muxes_offs]);\n }\n \n-/* CG functions */\n+/* infrasys functions */\n \n-static int mtk_clk_gate_enable(struct clk *clk)\n+static int mtk_clk_infrasys_enable(struct clk *clk)\n {\n \tstruct mtk_cg_priv *priv = dev_get_priv(clk->dev);\n \tint id = mtk_clk_get_id(clk);\n \tconst struct mtk_gate *gate;\n \n-\tif (id < priv->tree->gates_offs)\n-\t\treturn -EINVAL;\n+\t/* MUX handling */\n+\tif (!priv->tree->gates || id < priv->tree->gates_offs)\n+\t\treturn mtk_clk_mux_enable(clk);\n \n-\tgate = &priv->gates[id - priv->tree->gates_offs];\n+\tgate = &priv->tree->gates[id - priv->tree->gates_offs];\n \treturn mtk_gate_enable(priv->base, gate);\n }\n \n-static int mtk_clk_infrasys_enable(struct clk *clk)\n+static int mtk_clk_infrasys_disable(struct clk *clk)\n {\n \tstruct mtk_cg_priv *priv = dev_get_priv(clk->dev);\n \tint id = mtk_clk_get_id(clk);\n@@ -684,13 +601,99 @@ static int mtk_clk_infrasys_enable(struct clk *clk)\n \n \t/* MUX handling */\n \tif (!priv->tree->gates || id < priv->tree->gates_offs)\n-\t\treturn mtk_clk_mux_enable(clk);\n+\t\treturn mtk_clk_mux_disable(clk);\n \n \tgate = &priv->tree->gates[id - priv->tree->gates_offs];\n-\treturn mtk_gate_enable(priv->base, gate);\n+\treturn mtk_gate_disable(priv->base, gate);\n }\n \n-static int mtk_clk_gate_disable(struct clk *clk)\n+static ulong mtk_infrasys_get_factor_rate(struct clk *clk, u32 off)\n+{\n+\tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n+\tconst struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off];\n+\tulong rate;\n+\n+\tswitch (fdiv->flags & CLK_PARENT_MASK) {\n+\tcase CLK_PARENT_TOPCKGEN:\n+\t\trate = mtk_clk_find_parent_rate(clk, fdiv->parent,\n+\t\t\t\t\t\tpriv->parent);\n+\t\tbreak;\n+\tcase CLK_PARENT_XTAL:\n+\t\trate = priv->tree->xtal_rate;\n+\t\tbreak;\n+\tdefault:\n+\t\trate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);\n+\t}\n+\n+\treturn mtk_factor_recalc_rate(fdiv, rate);\n+}\n+\n+static ulong mtk_infrasys_get_mux_rate(struct clk *clk, u32 off)\n+{\n+\tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n+\tconst struct mtk_composite *mux = &priv->tree->muxes[off];\n+\tu32 index;\n+\n+\tindex = readl(priv->base + mux->mux_reg);\n+\tindex &= mux->mux_mask << mux->mux_shift;\n+\tindex = index >> mux->mux_shift;\n+\n+\t/*\n+\t * Parents can be either from TOPCKGEN or INFRACFG,\n+\t * inspect the mtk_parent struct to check the source\n+\t */\n+\tif (mux->flags & CLK_PARENT_MIXED) {\n+\t\tconst struct mtk_parent *parent = &mux->parent_flags[index];\n+\n+\t\treturn mtk_find_parent_rate(priv, clk, parent->id, parent->flags);\n+\t}\n+\n+\tif (mux->parent[index] == CLK_XTAL &&\n+\t !(priv->tree->flags & CLK_BYPASS_XTAL))\n+\t\treturn priv->tree->xtal_rate;\n+\n+\treturn mtk_find_parent_rate(priv, clk, mux->parent[index], mux->flags);\n+}\n+\n+static ulong mtk_infrasys_get_rate(struct clk *clk)\n+{\n+\tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n+\tint id = mtk_clk_get_id(clk);\n+\tulong rate;\n+\n+\tif (id < priv->tree->fdivs_offs) {\n+\t\trate = priv->tree->fclks[id].rate;\n+\t} else if (id < priv->tree->muxes_offs) {\n+\t\trate = mtk_infrasys_get_factor_rate(clk, id -\n+\t\t\t\t\t\t priv->tree->fdivs_offs);\n+\t/* No gates defined or ID is a MUX */\n+\t} else if (!priv->tree->gates || id < priv->tree->gates_offs) {\n+\t\trate = mtk_infrasys_get_mux_rate(clk, id -\n+\t\t\t\t\t\t priv->tree->muxes_offs);\n+\t/* Only valid with muxes + gates implementation */\n+\t} else {\n+\t\tstruct udevice *parent = NULL;\n+\t\tconst struct mtk_gate *gate;\n+\n+\t\tgate = &priv->tree->gates[id - priv->tree->gates_offs];\n+\t\tif (gate->flags & CLK_PARENT_TOPCKGEN)\n+\t\t\tparent = priv->parent;\n+\t\t/*\n+\t\t * Assume xtal_rate to be declared if some gates have\n+\t\t * XTAL as parent\n+\t\t */\n+\t\telse if (gate->flags & CLK_PARENT_XTAL)\n+\t\t\treturn priv->tree->xtal_rate;\n+\n+\t\trate = mtk_clk_find_parent_rate(clk, gate->parent, parent);\n+\t}\n+\n+\treturn rate;\n+}\n+\n+/* CG functions */\n+\n+static int mtk_clk_gate_enable(struct clk *clk)\n {\n \tstruct mtk_cg_priv *priv = dev_get_priv(clk->dev);\n \tint id = mtk_clk_get_id(clk);\n@@ -700,20 +703,19 @@ static int mtk_clk_gate_disable(struct clk *clk)\n \t\treturn -EINVAL;\n \n \tgate = &priv->gates[id - priv->tree->gates_offs];\n-\treturn mtk_gate_disable(priv->base, gate);\n+\treturn mtk_gate_enable(priv->base, gate);\n }\n \n-static int mtk_clk_infrasys_disable(struct clk *clk)\n+static int mtk_clk_gate_disable(struct clk *clk)\n {\n \tstruct mtk_cg_priv *priv = dev_get_priv(clk->dev);\n \tint id = mtk_clk_get_id(clk);\n \tconst struct mtk_gate *gate;\n \n-\t/* MUX handling */\n-\tif (!priv->tree->gates || id < priv->tree->gates_offs)\n-\t\treturn mtk_clk_mux_disable(clk);\n+\tif (id < priv->tree->gates_offs)\n+\t\treturn -EINVAL;\n \n-\tgate = &priv->tree->gates[id - priv->tree->gates_offs];\n+\tgate = &priv->gates[id - priv->tree->gates_offs];\n \treturn mtk_gate_disable(priv->base, gate);\n }\n \n","prefixes":["4/8"]}