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UNSPEC_F2CVTL): Added new unspecs.\n\t(FP8CVT_UNS): Extended int_iterator.\n\t(fp8_cvt_uns_op): Likewise.\n\ngcc/testsuite/\n\t* g++.target/aarch64/sme2/aarch64-sme2-acle-asm.exp: Use tuning flag\n\tto reduce churn in testsuites.\n\t* gcc.target/aarch64/sme2/aarch64-sme2-acle-asm.exp: Likewise.\n\t* gcc.target/aarch64/sme2/acle-asm/cvt_mf8_x2.c: Added test file.\n\t* gcc.target/aarch64/sme2/acle-asm/cvtl_mf8_x2.c: Likewise.\n\t* gcc.target/aarch64/sve/acle/asm/test_sve_acle.h (TEST_X2_WIDE): Added\n\tfpm0 argument for intrinsics.\n---\n .../aarch64/aarch64-sve-builtins-sve2.cc | 2 +\n .../aarch64/aarch64-sve-builtins-sve2.def | 8 ++++\n .../aarch64/aarch64-sve-builtins-sve2.h | 2 +\n gcc/config/aarch64/aarch64-sve-builtins.cc | 3 +-\n gcc/config/aarch64/aarch64-sve2.md | 10 ++++\n gcc/config/aarch64/aarch64.h | 2 +\n gcc/config/aarch64/iterators.md | 6 +++\n .../aarch64/sme2/aarch64-sme2-acle-asm.exp | 3 +-\n .../aarch64/sme2/aarch64-sme2-acle-asm.exp | 3 +-\n .../aarch64/sme2/acle-asm/cvt_mf8_x2.c | 47 +++++++++++++++++++\n .../aarch64/sme2/acle-asm/cvtl_mf8_x2.c | 47 +++++++++++++++++++\n .../aarch64/sve/acle/asm/test_sve_acle.h | 1 +\n 12 files changed, 131 insertions(+), 3 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtl_mf8_x2.c","diff":"diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc\nindex 95c5ed81d61..ee392c3a745 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc\n@@ -1020,6 +1020,8 @@ FUNCTION (svclamp, svclamp_impl,)\n FUNCTION (svcvt1, svcvt_fp8_impl, (UNSPEC_F1CVT))\n FUNCTION (svcvt2, svcvt_fp8_impl, (UNSPEC_F2CVT))\n FUNCTION (svcvtl, svcvtl_impl,)\n+FUNCTION (svcvtl1, svcvt_fp8_impl, (UNSPEC_F1CVTL))\n+FUNCTION (svcvtl2, svcvt_fp8_impl, (UNSPEC_F2CVTL))\n FUNCTION (svcvtlt1, svcvt_fp8_impl, (UNSPEC_F1CVTLT))\n FUNCTION (svcvtlt2, svcvt_fp8_impl, (UNSPEC_F2CVTLT))\n FUNCTION (svcvtlt, unspec_based_function, (-1, -1, UNSPEC_COND_FCVTLT))\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def\nindex 7075e3ff123..c271b97de87 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def\n@@ -418,3 +418,11 @@ DEF_SVE_FUNCTION_GS_FPM (svdot_lane, ternary_mfloat8_lane_group_selection, s_flo\n DEF_SVE_FUNCTION_GS_FPM (svdot, ternary_mfloat8, h_float_mf8, none, none, set)\n DEF_SVE_FUNCTION_GS_FPM (svdot_lane, ternary_mfloat8_lane_group_selection, h_float_mf8, none, none, set)\n #undef REQUIRED_EXTENSIONS\n+\n+#define REQUIRED_EXTENSIONS \\\n+ streaming_only (AARCH64_FL_SME2 | AARCH64_FL_FP8)\n+DEF_SVE_FUNCTION_GS_FPM (svcvt1, unary_convert, cvt_mf8, x2, none, set)\n+DEF_SVE_FUNCTION_GS_FPM (svcvt2, unary_convert, cvt_mf8, x2, none, set)\n+DEF_SVE_FUNCTION_GS_FPM (svcvtl1, unary_convert, cvt_mf8, x2, none, set)\n+DEF_SVE_FUNCTION_GS_FPM (svcvtl2, unary_convert, cvt_mf8, x2, none, set)\n+#undef REQUIRED_EXTENSIONS\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.h b/gcc/config/aarch64/aarch64-sve-builtins-sve2.h\nindex 6d7d0af2641..7c1745f5c9e 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.h\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.h\n@@ -64,6 +64,8 @@ namespace aarch64_sve\n extern const function_base *const svcvt1;\n extern const function_base *const svcvt2;\n extern const function_base *const svcvtl;\n+ extern const function_base *const svcvtl1;\n+ extern const function_base *const svcvtl2;\n extern const function_base *const svcvtlt;\n extern const function_base *const svcvtlt1;\n extern const function_base *const svcvtlt2;\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc b/gcc/config/aarch64/aarch64-sve-builtins.cc\nindex e8eeedb4d36..03481ee4a77 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins.cc\n+++ b/gcc/config/aarch64/aarch64-sve-builtins.cc\n@@ -3207,7 +3207,8 @@ function_resolver::resolve_unary (type_class_index merge_tclass,\n /* Handle convert-like functions in which the first type suffix is\n explicit. */\n if (type_suffix_ids[0] != NUM_TYPE_SUFFIXES)\n- return resolve_to (mode_suffix_id, type_suffix_ids[0], type);\n+ return resolve_to (mode_suffix_id, type_suffix_ids[0], type,\n+\t\t group_suffix_id);\n \n return resolve_to (mode_suffix_id, type);\n }\ndiff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md\nindex 91091835182..ab8098d3327 100644\n--- a/gcc/config/aarch64/aarch64-sve2.md\n+++ b/gcc/config/aarch64/aarch64-sve2.md\n@@ -3591,6 +3591,16 @@ (define_insn \"@aarch64_sve_cvtl\"\n [(set_attr \"sve_type\" \"sve_fp_cvt\")]\n )\n \n+(define_insn \"@aarch64_sve2_fp8_cvt_\"\n+ [(set (match_operand:SVE_FULL_HFx2 0 \"aligned_register_operand\" \"=Uw2\")\n+\t(unspec:SVE_FULL_HFx2\n+\t [(match_operand:VNx16QI 1 \"register_operand\" \"w\")\n+\t (reg:DI FPM_REGNUM)]\n+\t FP8CVT_UNS))]\n+ \"TARGET_SSME2_FP8\"\n+ \"\\t%0, %1.b\"\n+)\n+\n ;; -------------------------------------------------------------------------\n ;; ---- [FP<-FP] Multi-vector narrowing conversions\n ;; -------------------------------------------------------------------------\ndiff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h\nindex 8e1018e4014..e3eb807fb53 100644\n--- a/gcc/config/aarch64/aarch64.h\n+++ b/gcc/config/aarch64/aarch64.h\n@@ -538,6 +538,8 @@ through +ssve-fp8dot2. */\n \t\t(TARGET_SVE2 && TARGET_FP8DOT2) || TARGET_STREAMING) \\\n \t\t&& (AARCH64_HAVE_ISA(SSVE_FP8DOT2) || TARGET_NON_STREAMING))\n \n+#define TARGET_SSME2_FP8 (TARGET_FP8 && TARGET_STREAMING_SME2)\n+\n /* Standard register usage. */\n \n /* 31 64-bit general purpose registers R0-R30:\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex c5120c37afa..026c3101e38 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -1055,8 +1055,10 @@ (define_c_enum \"unspec\"\n UNSPEC_EORBT\t; Used in aarch64-sve2.md.\n UNSPEC_EORTB\t; Used in aarch64-sve2.md.\n UNSPEC_F1CVT\t; Used in aarch64-sve2.md.\n+ UNSPEC_F1CVTL\t; Used in aarch64-sve2.md.\n UNSPEC_F1CVTLT\t; Used in aarch64-sve2.md.\n UNSPEC_F2CVT\t; Used in aarch64-sve2.md.\n+ UNSPEC_F2CVTL\t; Used in aarch64-sve2.md.\n UNSPEC_F2CVTLT\t; Used in aarch64-sve2.md.\n UNSPEC_FADDP\t; Used in aarch64-sve2.md.\n UNSPEC_FCVTNB\t; Used in aarch64-sve2.md.\n@@ -4044,6 +4046,8 @@ (define_int_iterator SET_FPSCR\n (define_int_iterator FP8CVT_UNS\n [UNSPEC_F1CVT\n UNSPEC_F2CVT\n+ UNSPEC_F1CVTL\n+ UNSPEC_F2CVTL\n UNSPEC_F1CVTLT\n UNSPEC_F2CVTLT])\n \n@@ -5187,6 +5191,8 @@ (define_int_attr atomic_ldoptab\n (define_int_attr fp8_cvt_uns_op\n [(UNSPEC_F1CVT \"f1cvt\")\n (UNSPEC_F2CVT \"f2cvt\")\n+ (UNSPEC_F1CVTL \"f1cvtl\")\n+ (UNSPEC_F2CVTL \"f2cvtl\")\n (UNSPEC_F1CVTLT \"f1cvtlt\")\n (UNSPEC_F2CVTLT \"f2cvtlt\")])\n \ndiff --git a/gcc/testsuite/g++.target/aarch64/sme2/aarch64-sme2-acle-asm.exp b/gcc/testsuite/g++.target/aarch64/sme2/aarch64-sme2-acle-asm.exp\nindex 334b1108ddc..b182f9d4a96 100644\n--- a/gcc/testsuite/g++.target/aarch64/sme2/aarch64-sme2-acle-asm.exp\n+++ b/gcc/testsuite/g++.target/aarch64/sme2/aarch64-sme2-acle-asm.exp\n@@ -39,7 +39,8 @@ if { [check_effective_target_aarch64_sme2] } {\n \n # Turn off any codegen tweaks by default that may affect expected assembly.\n # Tests relying on those should turn them on explicitly.\n-set sme2_flags \"$sme2_flags -mtune=generic -moverride=tune=none\"\n+# Reduce testsuite churn when writing to fmpr\n+set sme2_flags \"$sme2_flags -mtune=generic -moverride=tune=none -moverride=tune=cheap_fpmr_write\"\n \n global gcc_runtest_parallelize_limit_minor\n if { [info exists gcc_runtest_parallelize_limit_minor] } {\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/aarch64-sme2-acle-asm.exp b/gcc/testsuite/gcc.target/aarch64/sme2/aarch64-sme2-acle-asm.exp\nindex 6bd8784779c..256c484bb84 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sme2/aarch64-sme2-acle-asm.exp\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/aarch64-sme2-acle-asm.exp\n@@ -39,7 +39,8 @@ if { [check_effective_target_aarch64_sme2] } {\n \n # Turn off any codegen tweaks by default that may affect expected assembly.\n # Tests relying on those should turn them on explicitly.\n-set sme2_flags \"$sme2_flags -mtune=generic -moverride=tune=none\"\n+# Reduce testsuite churn when writing to fmpr\n+set sme2_flags \"$sme2_flags -mtune=generic -moverride=tune=none -moverride=tune=cheap_fpmr_write\"\n \n global gcc_runtest_parallelize_limit_minor\n if { [info exists gcc_runtest_parallelize_limit_minor] } {\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_x2.c\nnew file mode 100644\nindex 00000000000..0fb20c8edf8\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_x2.c\n@@ -0,0 +1,47 @@\n+/* { dg-do assemble { target { aarch64_asm_fp8_ok && aarch64_asm_sme2_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_fp8_ok && aarch64_asm_sme2_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+\n+#pragma GCC target \"+fp8\"\n+\n+/*\n+** cvt1_f16_mf8_x2_fpm:\n+**\tmsr\tfpmr, x0\n+**\tf1cvt\t{z0\\.h - z1\\.h}, z0\\.b\n+**\tret\n+*/\n+TEST_X2_WIDE (cvt1_f16_mf8_x2_fpm, svfloat16x2_t, svmfloat8_t,\n+\t z0_res = svcvt1_f16_mf8_x2_fpm (z0, fpm0),\n+\t z0_res = svcvt1_f16_x2_fpm (z0, fpm0))\n+\n+/*\n+** cvt1_bf16_mf8_x2_fpm:\n+**\tmsr\tfpmr, x0\n+**\tbf1cvt\t{z0\\.h - z1\\.h}, z0\\.b\n+**\tret\n+*/\n+TEST_X2_WIDE (cvt1_bf16_mf8_x2_fpm, svbfloat16x2_t, svmfloat8_t,\n+\t z0_res = svcvt1_bf16_mf8_x2_fpm (z0, fpm0),\n+\t z0_res = svcvt1_bf16_x2_fpm (z0, fpm0))\n+\n+/*\n+** cvt2_f16_mf8_x2_fpm:\n+**\tmsr\tfpmr, x0\n+**\tf2cvt\t{z0\\.h - z1\\.h}, z0\\.b\n+**\tret\n+*/\n+TEST_X2_WIDE (cvt2_f16_mf8_x2_fpm, svfloat16x2_t, svmfloat8_t,\n+\t z0_res = svcvt2_f16_mf8_x2_fpm (z0, fpm0),\n+\t z0_res = svcvt2_f16_x2_fpm (z0, fpm0))\n+\n+/*\n+** cvt2_bf16_mf8_x2_fpm:\n+**\tmsr\tfpmr, x0\n+**\tbf2cvt\t{z0\\.h - z1\\.h}, z0\\.b\n+**\tret\n+*/\n+TEST_X2_WIDE (cvt2_bf16_mf8_x2_fpm, svbfloat16x2_t, svmfloat8_t,\n+\t z0_res = svcvt2_bf16_mf8_x2_fpm (z0, fpm0),\n+\t z0_res = svcvt2_bf16_x2_fpm (z0, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtl_mf8_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtl_mf8_x2.c\nnew file mode 100644\nindex 00000000000..8a8326bd068\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtl_mf8_x2.c\n@@ -0,0 +1,47 @@\n+/* { dg-do assemble { target { aarch64_asm_fp8_ok && aarch64_asm_sme2_ok } } } */\n+/* { dg-do compile { target { ! { aarch64_asm_fp8_ok && aarch64_asm_sme2_ok } } } } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+\n+#pragma GCC target \"+fp8\"\n+\n+/*\n+** cvtl1_f16_mf8_x2_fpm:\n+**\tmsr\tfpmr, x0\n+**\tf1cvtl\t{z0\\.h - z1\\.h}, z0\\.b\n+**\tret\n+*/\n+TEST_X2_WIDE (cvtl1_f16_mf8_x2_fpm, svfloat16x2_t, svmfloat8_t,\n+\t z0_res = svcvtl1_f16_mf8_x2_fpm (z0, fpm0),\n+\t z0_res = svcvtl1_f16_x2_fpm (z0, fpm0))\n+\n+/*\n+** cvtl1_bf16_mf8_x2_fpm:\n+**\tmsr\tfpmr, x0\n+**\tbf1cvtl\t{z0\\.h - z1\\.h}, z0\\.b\n+**\tret\n+*/\n+TEST_X2_WIDE (cvtl1_bf16_mf8_x2_fpm, svbfloat16x2_t, svmfloat8_t,\n+\t z0_res = svcvtl1_bf16_mf8_x2_fpm (z0, fpm0),\n+\t z0_res = svcvtl1_bf16_x2_fpm (z0, fpm0))\n+\n+/*\n+** cvtl2_f16_mf8_x2_fpm:\n+**\tmsr\tfpmr, x0\n+**\tf2cvtl\t{z0\\.h - z1\\.h}, z0\\.b\n+**\tret\n+*/\n+TEST_X2_WIDE (cvtl2_f16_mf8_x2_fpm, svfloat16x2_t, svmfloat8_t,\n+\t z0_res = svcvtl2_f16_mf8_x2_fpm (z0, fpm0),\n+\t z0_res = svcvtl2_f16_x2_fpm (z0, fpm0))\n+\n+/*\n+** cvtl2_bf16_mf8_x2_fpm:\n+**\tmsr\tfpmr, x0\n+**\tbf2cvtl\t{z0\\.h - z1\\.h}, z0\\.b\n+**\tret\n+*/\n+TEST_X2_WIDE (cvtl2_bf16_mf8_x2_fpm, svbfloat16x2_t, svmfloat8_t,\n+\t z0_res = svcvtl2_bf16_mf8_x2_fpm (z0, fpm0),\n+\t z0_res = svcvtl2_bf16_x2_fpm (z0, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h\nindex 0adb39ad8b2..7c156c4cf2a 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h\n@@ -767,6 +767,7 @@\n #define TEST_X2_WIDE(NAME, TTYPE, ZTYPE, CODE1, CODE2)\t\t\\\n PROTO (NAME, void, ())\t\t\t\t\t\\\n {\t\t\t\t\t\t\t\t\\\n+ register fpm_t fpm0 __asm (\"x0\");\t\t\t\t\\\n register ZTYPE z0 __asm (\"z0\");\t\t\t\t\\\n register ZTYPE z5 __asm (\"z5\");\t\t\t\t\\\n register TTYPE z6 __asm (\"z6\");\t\t\t\t\\\n","prefixes":["v5","3/9"]}