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DB1PEPF000509EF.eurprd03.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"This patch adds the following intrinsics (all __arm_streaming only) along with\nasm tests for them.\n\nBFCVT, FCVT Convert to packed 8-bit floating-point format:\n- svmfloat8_t svcvt_mf8[_f16_x2]_fpm(svfloat16x2_t zn, fpm_t fpm)\n- svmfloat8_t svcvt_mf8[_bf16_x2]_fpm(svbfloat16x2_t zn, fpm_t fpm)\n- svmfloat8_t svcvt_mf8[_f32_x4]_fpm(svfloat32x4_t zn, fpm_t fpm)\n\nFCVTN Convert to interleaved 8-bit floating-point format.\n- svmfloat8_t svcvtn_mf8[_f32_x4]_fpm(svfloat32x4_t zn, fpm_t fpm)\n\ngcc/\n\t* config/aarch64/aarch64-sve-builtins-base.cc (svcvt_impl): Update to\n\thandle fp8 cases.\n\t* config/aarch64/aarch64-sve-builtins-sve2.def (svcvt, svcvtn): Added\n\tDEF_SVE_FUNCTION_GS_FPM instances.\n\t* config/aarch64/aarch64-sve2.md\n\t(@aarch64_sve2_fp8_cvtn): Updated define_insn for additional case.\n\t(@aarch64_sme2_fp8_cvt): Added new define_insn.\n\t* config/aarch64/iterators.md (VNx16F_NARROW): Added new iterator to\n\thandle narrowing SVE floating point operations.\n\t(UNSPEC_FCVT): Added new unspec.\n\ngcc/testsuite/\n\t* gcc.target/aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c: Added test file.\n\t* gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c: Likewise.\n\t* gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c: Likewise.\n\t* gcc.target/aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c: Likewise.\n\t* gcc.target/aarch64/sve/acle/asm/test_sve_acle.h\n\t(TEST_X2_NARROW): Added fpm0 argument for intrinsics.\n\t(TEST_X4_NARROW): Likewise.\n---\n .../aarch64/aarch64-sve-builtins-base.cc | 26 ++++---\n .../aarch64/aarch64-sve-builtins-sve2.def | 3 +\n gcc/config/aarch64/aarch64-sve2.md | 14 +++-\n gcc/config/aarch64/iterators.md | 4 ++\n .../aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c | 56 +++++++++++++++\n .../aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c | 56 +++++++++++++++\n .../aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c | 72 +++++++++++++++++++\n .../aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c | 72 +++++++++++++++++++\n .../aarch64/sve/acle/asm/test_sve_acle.h | 2 +\n 9 files changed, 293 insertions(+), 12 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c","diff":"diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc\nindex ecc06877cac..622485effb3 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc\n@@ -779,17 +779,23 @@ public:\n {\n \tmachine_mode mode0 = e.result_mode ();\n \tmachine_mode mode1 = GET_MODE (e.args[0]);\n-\tconvert_optab optab;\n-\tif (e.type_suffix (0).integer_p)\n-\t optab = e.type_suffix (0).unsigned_p ? ufix_optab : sfix_optab;\n-\telse if (e.type_suffix (1).integer_p)\n-\t optab = e.type_suffix (1).unsigned_p ? ufloat_optab : sfloat_optab;\n-\telse if (e.type_suffix (0).element_bits\n-\t\t < e.type_suffix (1).element_bits)\n-\t optab = trunc_optab;\n+\tif (e.fpm_mode == aarch64_sve::FPM_set)\n+\t icode = code_for_aarch64_sme2_fp8_cvt (mode1);\n \telse\n-\t optab = sext_optab;\n-\ticode = convert_optab_handler (optab, mode0, mode1);\n+\t {\n+\t convert_optab optab;\n+\t if (e.type_suffix (0).integer_p)\n+\t optab = e.type_suffix (0).unsigned_p ? ufix_optab : sfix_optab;\n+\t else if (e.type_suffix (1).integer_p)\n+\t optab = e.type_suffix (1).unsigned_p ? ufloat_optab\n+\t\t\t\t\t\t : sfloat_optab;\n+\t else if (e.type_suffix (0).element_bits\n+\t\t < e.type_suffix (1).element_bits)\n+\t optab = trunc_optab;\n+\t else\n+\t optab = sext_optab;\n+\t icode = convert_optab_handler (optab, mode0, mode1);\n+\t }\n \tgcc_assert (icode != CODE_FOR_nothing);\n \treturn e.use_exact_insn (icode);\n }\ndiff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def\nindex c271b97de87..869e006ffde 100644\n--- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def\n+++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def\n@@ -421,6 +421,9 @@ DEF_SVE_FUNCTION_GS_FPM (svdot_lane, ternary_mfloat8_lane_group_selection, h_flo\n \n #define REQUIRED_EXTENSIONS \\\n streaming_only (AARCH64_FL_SME2 | AARCH64_FL_FP8)\n+DEF_SVE_FUNCTION_GS_FPM (svcvt, unary_convertxn_narrow, cvtn_mf8, x2, none, set)\n+DEF_SVE_FUNCTION_GS_FPM (svcvt, unary_convertxn_narrow, cvtnx_mf8, x4, none, set)\n+DEF_SVE_FUNCTION_GS_FPM (svcvtn, unary_convertxn_narrow, cvtnx_mf8, x4, none, set)\n DEF_SVE_FUNCTION_GS_FPM (svcvt1, unary_convert, cvt_mf8, x2, none, set)\n DEF_SVE_FUNCTION_GS_FPM (svcvt2, unary_convert, cvt_mf8, x2, none, set)\n DEF_SVE_FUNCTION_GS_FPM (svcvtl1, unary_convert, cvt_mf8, x2, none, set)\ndiff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md\nindex ab8098d3327..da7a7a3c23c 100644\n--- a/gcc/config/aarch64/aarch64-sve2.md\n+++ b/gcc/config/aarch64/aarch64-sve2.md\n@@ -3635,10 +3635,10 @@ (define_insn \"@aarch64_sve_cvtn\"\n (define_insn \"@aarch64_sve2_fp8_cvtn\"\n [(set (match_operand:VNx16QI 0 \"register_operand\" \"=w\")\n \t(unspec:VNx16QI\n-\t [(match_operand:SVE_FULL_HFx2 1 \"aligned_register_operand\" \"Uw2\")\n+\t [(match_operand:VNx16F_NARROW 1 \"aligned_register_operand\" \"Uw\")\n \t (reg:DI FPM_REGNUM)]\n \t UNSPEC_FP8FCVTN))]\n- \"TARGET_SSVE_FP8\"\n+ \"mode == VNx16SFmode ? TARGET_SSME2_FP8 : TARGET_STREAMING_SME2\"\n \"fcvtn\\t%0.b, %1\"\n [(set_attr \"sve_type\" \"sve_fp_cvt\")]\n )\n@@ -3666,6 +3666,16 @@ (define_insn \"@aarch64_sve_cvtnt\"\n [(set_attr \"sve_type\" \"sve_fp_cvt\")]\n )\n \n+(define_insn \"@aarch64_sme2_fp8_cvt\"\n+ [(set (match_operand:VNx16QI 0 \"register_operand\" \"=w\")\n+\t(unspec:VNx16QI\n+\t [(match_operand:VNx16F_NARROW 1 \"aligned_register_operand\" \"Uw\")\n+\t (reg:DI FPM_REGNUM)]\n+\t UNSPEC_FCVT))]\n+ \"TARGET_SSME2_FP8\"\n+ \"fcvt\\t%0.b, %1\"\n+)\n+\n ;; -------------------------------------------------------------------------\n ;; ---- [FP<-INT] Multi-vector conversions\n ;; -------------------------------------------------------------------------\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex 026c3101e38..e6f59d22d0c 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -712,6 +712,9 @@ (define_mode_iterator VNx4_WIDE [VNx4SI])\n (define_mode_iterator VNx2_NARROW [VNx2QI VNx2HI VNx2SI])\n (define_mode_iterator VNx2_WIDE [VNx2DI])\n \n+;; Used for narrowing SVE floating point operations.\n+(define_mode_iterator VNx16F_NARROW [VNx16BF VNx16HF VNx16SF])\n+\n ;; All SVE predicate modes.\n (define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])\n \n@@ -1061,6 +1064,7 @@ (define_c_enum \"unspec\"\n UNSPEC_F2CVTL\t; Used in aarch64-sve2.md.\n UNSPEC_F2CVTLT\t; Used in aarch64-sve2.md.\n UNSPEC_FADDP\t; Used in aarch64-sve2.md.\n+ UNSPEC_FCVT\t\t; Used in aarch64-sve2.md.\n UNSPEC_FCVTNB\t; Used in aarch64-sve2.md.\n UNSPEC_FCVTNT\t; Used in aarch64-sve2.md.\n UNSPEC_FMAXNMP\t; Used in aarch64-sve2.md.\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c\nnew file mode 100644\nindex 00000000000..bdda0fd36d6\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_bf16_x2.c\n@@ -0,0 +1,56 @@\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#pragma GCC target \"+fp8+bf16\"\n+#include \"test_sme2_acle.h\"\n+\n+/*\n+** cvt_z0_z0:\n+**\tmsr\tfpmr, x0\n+**\tbfcvt\tz0\\.b, {z0\\.h - z1\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z0_z0, svbfloat16x2_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_bf16_x2_fpm (z0, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvt_z0_z6:\n+**\tmsr\tfpmr, x0\n+**\tbfcvt\tz0\\.b, {z6\\.h - z7\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z0_z6, svbfloat16x2_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_bf16_x2_fpm (z6, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z6, fpm0))\n+\n+/*\n+** cvt_z0_z29:\n+**\tmsr\tfpmr, x0\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tbfcvt\tz0\\.b, [^\\n]+\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z0_z29, svbfloat16x2_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_bf16_x2_fpm (z29, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z29, fpm0))\n+\n+/*\n+** cvt_z5_z0:\n+**\tmsr\tfpmr, x0\n+**\tbfcvt\tz5\\.b, {z0\\.h - z1\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z5_z0, svbfloat16x2_t, svmfloat8_t,\n+\t\tz5 = svcvt_mf8_bf16_x2_fpm (z0, fpm0),\n+\t\tz5 = svcvt_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvt_z22_z16:\n+**\tmsr\tfpmr, x0\n+**\tbfcvt\tz22\\.b, {z16\\.h - z17\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z22_z16, svbfloat16x2_t, svmfloat8_t,\n+\t\tz22 = svcvt_mf8_bf16_x2_fpm (z16, fpm0),\n+\t\tz22 = svcvt_mf8_fpm (z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c\nnew file mode 100644\nindex 00000000000..93792e90945\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f16_x2.c\n@@ -0,0 +1,56 @@\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+fp8\"\n+\n+/*\n+** cvt_z0_z0:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz0\\.b, {z0\\.h - z1\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z0_z0, svfloat16x2_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_f16_x2_fpm (z0, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvt_z0_z6:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz0\\.b, {z6\\.h - z7\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z0_z6, svfloat16x2_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_f16_x2_fpm (z6, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z6, fpm0))\n+\n+/*\n+** cvt_z0_z29:\n+**\tmsr\tfpmr, x0\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfcvt\tz0\\.b, {z0\\.h - z1\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z0_z29, svfloat16x2_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_f16_x2_fpm (z29, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z29, fpm0))\n+\n+/*\n+** cvt_z5_z0:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz5\\.b, {z0\\.h - z1\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z5_z0, svfloat16x2_t, svmfloat8_t,\n+\t\tz5 = svcvt_mf8_f16_x2_fpm (z0, fpm0),\n+\t\tz5 = svcvt_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvt_z22_z16:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz22\\.b, {z16\\.h - z17\\.h}\n+**\tret\n+*/\n+TEST_X2_NARROW (cvt_z22_z16, svfloat16x2_t, svmfloat8_t,\n+\t\tz22 = svcvt_mf8_f16_x2_fpm (z16, fpm0),\n+\t\tz22 = svcvt_mf8_fpm (z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c\nnew file mode 100644\nindex 00000000000..a9ee10de0df\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvt_mf8_f32_x4.c\n@@ -0,0 +1,72 @@\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+fp8\"\n+\n+/*\n+** cvt_z0_z0:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz0\\.b, {z0\\.s - z3\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvt_z0_z0, svfloat32x4_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_f32_x4_fpm (z0, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvt_z0_z4:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz0\\.b, {z4\\.s - z7\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvt_z0_z4, svfloat32x4_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_f32_x4_fpm (z4, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z4, fpm0))\n+\n+/*\n+** cvt_z0_z21:\n+**\tmsr\tfpmr, x0\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfcvt\tz0\\.b, [^\\n]+\n+**\tret\n+*/\n+TEST_X4_NARROW (cvt_z0_z21, svfloat32x4_t, svmfloat8_t,\n+\t\tz0_res = svcvt_mf8_f32_x4_fpm (z21, fpm0),\n+\t\tz0_res = svcvt_mf8_fpm (z21, fpm0))\n+\n+/*\n+** cvt_z25_z26:\n+**\tmsr\tfpmr, x0\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfcvt\tz25\\.b, {z28\\.s - z31\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvt_z25_z26, svfloat32x4_t, svmfloat8_t,\n+\t\tz25 = svcvt_mf8_f32_x4_fpm (z26, fpm0),\n+\t\tz25 = svcvt_mf8_fpm (z26, fpm0))\n+\n+/*\n+** cvt_z25_z0:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz25\\.b, {z0\\.s - z3\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvt_z25_z0, svfloat32x4_t, svmfloat8_t,\n+\tz25 = svcvt_mf8_f32_x4_fpm (z0, fpm0),\n+\tz25 = svcvt_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvt_z22_z16:\n+**\tmsr\tfpmr, x0\n+**\tfcvt\tz22\\.b, {z16\\.s - z19\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvt_z22_z16, svfloat32x4_t, svmfloat8_t,\n+\tz22_res = svcvt_mf8_f32_x4_fpm (z16, fpm0),\n+\tz22_res = svcvt_mf8_fpm (z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c\nnew file mode 100644\nindex 00000000000..2d0bd7eda0e\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/cvtn_mf8_f32_x4.c\n@@ -0,0 +1,72 @@\n+/* { dg-final { check-function-bodies \"**\" \"\" \"-DCHECK_ASM\" } } */\n+\n+#include \"test_sme2_acle.h\"\n+#pragma GCC target \"+fp8\"\n+\n+/*\n+** cvtn_z0_z0:\n+**\tmsr\tfpmr, x0\n+**\tfcvtn\tz0\\.b, {z0\\.s - z3\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvtn_z0_z0, svfloat32x4_t, svmfloat8_t,\n+\t\tz0_res = svcvtn_mf8_f32_x4_fpm (z0, fpm0),\n+\t\tz0_res = svcvtn_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvtn_z0_z4:\n+**\tmsr\tfpmr, x0\n+**\tfcvtn\tz0\\.b, {z4\\.s - z7\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvtn_z0_z4, svfloat32x4_t, svmfloat8_t,\n+\t\tz0_res = svcvtn_mf8_f32_x4_fpm (z4, fpm0),\n+\t\tz0_res = svcvtn_mf8_fpm (z4, fpm0))\n+\n+/*\n+** cvtn_z0_z21:\n+**\tmsr\tfpmr, x0\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfcvtn\tz0\\.b, [^\\n]+\n+**\tret\n+*/\n+TEST_X4_NARROW (cvtn_z0_z21, svfloat32x4_t, svmfloat8_t,\n+\t\tz0_res = svcvtn_mf8_f32_x4_fpm (z21, fpm0),\n+\t\tz0_res = svcvtn_mf8_fpm (z21, fpm0))\n+\n+/*\n+** cvtn_z25_z26:\n+**\tmsr\tfpmr, x0\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tmov\t[^\\n]+\n+**\tfcvtn\tz25\\.b, {z28\\.s - z31\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvtn_z25_z26, svfloat32x4_t, svmfloat8_t,\n+\t\tz25 = svcvtn_mf8_f32_x4_fpm (z26, fpm0),\n+\t\tz25 = svcvtn_mf8_fpm (z26, fpm0))\n+\n+/*\n+** cvtn_z25_z0:\n+**\tmsr\tfpmr, x0\n+**\tfcvtn\tz25\\.b, {z0\\.s - z3\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvtn_z25_z0, svfloat32x4_t, svmfloat8_t,\n+\tz25 = svcvtn_mf8_f32_x4_fpm (z0, fpm0),\n+\tz25 = svcvtn_mf8_fpm (z0, fpm0))\n+\n+/*\n+** cvtn_z22_z16:\n+**\tmsr\tfpmr, x0\n+**\tfcvtn\tz22\\.b, {z16\\.s - z19\\.s}\n+**\tret\n+*/\n+TEST_X4_NARROW (cvtn_z22_z16, svfloat32x4_t, svmfloat8_t,\n+\tz22_res = svcvtn_mf8_f32_x4_fpm (z16, fpm0),\n+\tz22_res = svcvtn_mf8_fpm (z16, fpm0))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h\nindex 7c156c4cf2a..8d4ed537c87 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/test_sve_acle.h\n@@ -733,6 +733,7 @@\n #define TEST_X2_NARROW(NAME, TTYPE, ZTYPE, CODE1, CODE2)\t\\\n PROTO (NAME, void, ())\t\t\t\t\t\\\n {\t\t\t\t\t\t\t\t\\\n+ register fpm_t fpm0 __asm (\"x0\");\t\t\t\t\\\n register TTYPE z0 __asm (\"z0\");\t\t\t\t\\\n register ZTYPE z5 __asm (\"z5\");\t\t\t\t\\\n register TTYPE z6 __asm (\"z6\");\t\t\t\t\\\n@@ -749,6 +750,7 @@\n #define TEST_X4_NARROW(NAME, TTYPE, ZTYPE, CODE1, CODE2)\t\\\n PROTO (NAME, void, ())\t\t\t\t\t\\\n {\t\t\t\t\t\t\t\t\\\n+ register fpm_t fpm0 __asm (\"x0\");\t\t\t\t\\\n register TTYPE z0 __asm (\"z0\");\t\t\t\t\\\n register TTYPE z4 __asm (\"z4\");\t\t\t\t\\\n register TTYPE z16 __asm (\"z16\");\t\t\t\t\\\n","prefixes":["v4","3/8"]}