{"id":2175537,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175537/?format=json","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.0/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20251218083326.644326-5-brian.ruley@gehealthcare.com>","date":"2025-12-18T08:33:23","name":"[v1,4/7] video: imx: ipuv3: fix camel cases","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"8204483360fd673ff1fe9266c9e60f1ebcbcd261","submitter":{"id":89422,"url":"http://patchwork.ozlabs.org/api/1.0/people/89422/?format=json","name":"Brian Ruley","email":"brian.ruley@gehealthcare.com"},"delegate":{"id":151988,"url":"http://patchwork.ozlabs.org/api/1.0/users/151988/?format=json","username":"festevam","first_name":"Fabio","last_name":"Estevam","email":"festevam@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20251218083326.644326-5-brian.ruley@gehealthcare.com/mbox/","series":[{"id":485836,"url":"http://patchwork.ozlabs.org/api/1.0/series/485836/?format=json","date":"2025-12-18T08:33:20","name":"Refactor i.MX IPU driver","version":1,"mbox":"http://patchwork.ozlabs.org/series/485836/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175537/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gehealthcare.com header.i=@gehealthcare.com\n header.a=rsa-sha256 header.s=selector1 header.b=VTkYHAjo;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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/* true = inverted */\n \tunsigned clk_pol : 1; /* true = rising edge */\n \tunsigned enable_pol : 1;\n-\tunsigned Hsync_pol : 1; /* true = active high */\n-\tunsigned Vsync_pol : 1;\n+\tunsigned hsync_pol : 1; /* true = active high */\n+\tunsigned vsync_pol : 1;\n } ipu_di_signal_cfg_t;\n \n-typedef enum { RGB, YCbCr, YUV } ipu_color_space_t;\n+typedef enum { RGB, YCBCR, YUV } ipu_color_space_t;\n \n /* Common IPU API */\n int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params);\n@@ -211,7 +211,7 @@ int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,\n \t\t\t\tu32 v_offset);\n \n void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,\n-\t\t\t u32 bufNum);\n+\t\t\t u32 buf_num);\n int32_t ipu_enable_channel(ipu_channel_t channel);\n int32_t ipu_disable_channel(ipu_channel_t channel);\n \n@@ -224,7 +224,7 @@ int32_t ipu_init_sync_panel(int disp, u32 pixel_clk, u16 width, u16 height,\n int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,\n \t\t\t\t u8 alpha);\n int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,\n-\t\t\t u32 colorKey);\n+\t\t\t u32 color_key);\n \n u32 bytes_per_pixel(u32 fmt);\n \ndiff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c\nindex 78bff87097e..6ce44e42349 100644\n--- a/drivers/video/imx/ipu_common.c\n+++ b/drivers/video/imx/ipu_common.c\n@@ -273,10 +273,10 @@ static inline int ipu_is_dmfc_chan(u32 dma_chan)\n \treturn ((dma_chan >= 23) && (dma_chan <= 29));\n }\n \n-static inline void ipu_ch_param_set_buffer(u32 ch, int bufNum,\n+static inline void ipu_ch_param_set_buffer(u32 ch, int buf_num,\n \t\t\t\t\t dma_addr_t phyaddr)\n {\n-\tipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29,\n+\tipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * buf_num, 29,\n \t\t\t phyaddr / 8);\n };\n \n@@ -1075,12 +1075,12 @@ int32_t ipu_enable_channel(ipu_channel_t channel)\n *\n * @param\ttype\t\tInput parameter which buffer to clear.\n *\n- * @param\tbufNum\t\tInput parameter for which buffer number clear\n+ * @param\tbuf_num\t\t Input parameter for which buffer number clear\n *\t\t\t\tready state.\n *\n */\n void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,\n-\t\t\t u32 bufNum)\n+\t\t\t u32 buf_num)\n {\n \tu32 dma_ch = channel_2_dma(channel, type);\n \n@@ -1088,7 +1088,7 @@ void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,\n \t\treturn;\n \n \t__raw_writel(0xF0000000, IPU_GPR); /* write one to clear */\n-\tif (bufNum == 0) {\n+\tif (buf_num == 0) {\n \t\tif (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {\n \t\t\t__raw_writel(idma_mask(dma_ch),\n \t\t\t\t IPU_CHA_BUF0_RDY(dma_ch));\n@@ -1212,7 +1212,7 @@ ipu_color_space_t format_to_colorspace(u32 fmt)\n \t\tbreak;\n \n \tdefault:\n-\t\treturn YCbCr;\n+\t\treturn YCBCR;\n \t\tbreak;\n \t}\n \treturn RGB;\ndiff --git a/drivers/video/imx/ipu_disp.c b/drivers/video/imx/ipu_disp.c\nindex af6daec7f64..89dead372cd 100644\n--- a/drivers/video/imx/ipu_disp.c\n+++ b/drivers/video/imx/ipu_disp.c\n@@ -1090,9 +1090,9 @@ int32_t ipu_init_sync_panel(int disp, u32 pixel_clk, u16 width, u16 height,\n \t\t\tipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5);\n \t\t}\n \n-\t\tif (sig.Hsync_pol)\n+\t\tif (sig.hsync_pol)\n \t\t\tdi_gen |= DI_GEN_POLARITY_2;\n-\t\tif (sig.Vsync_pol)\n+\t\tif (sig.vsync_pol)\n \t\t\tdi_gen |= DI_GEN_POLARITY_3;\n \n \t\tif (!sig.clk_pol)\n@@ -1181,7 +1181,7 @@ int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,\n *\n * @param\tenable\t\tBoolean to enable or disable color key\n *\n- * @param\tcolorKey\t24-bit RGB color for transparent color key.\n+ * @param\tcolor_key\t 24-bit RGB color for transparent color key.\n *\n * Return:\tReturns 0 on success or negative error code on fail\n */\ndiff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c\nindex 6c271490ba1..fb9d364d23a 100644\n--- a/drivers/video/imx/mxc_ipuv3_fb.c\n+++ b/drivers/video/imx/mxc_ipuv3_fb.c\n@@ -211,9 +211,9 @@ static int mxcfb_set_par(struct fb_info *fbi)\n \tif ((fbi->var.sync & FB_SYNC_EXT) || ext_clk_used)\n \t\tsig_cfg.ext_clk = 1;\n \tif (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)\n-\t\tsig_cfg.Hsync_pol = 1;\n+\t\tsig_cfg.hsync_pol = 1;\n \tif (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)\n-\t\tsig_cfg.Vsync_pol = 1;\n+\t\tsig_cfg.vsync_pol = 1;\n \tif (!(fbi->var.sync & FB_SYNC_CLK_LAT_FALL))\n \t\tsig_cfg.clk_pol = 1;\n \tif (fbi->var.sync & FB_SYNC_DATA_INVERT)\n","prefixes":["v1","4/7"]}