{"id":2175533,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175533/?format=json","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.0/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20251218-pci-dwc-suspend-rework-v2-1-5a7778c6094a@oss.qualcomm.com>","date":"2025-12-18T12:04:52","name":"[v2,1/2] PCI: dwc: Skip PME_Turn_Off broadcast and L2/L3 transition during suspend if link is not up","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"07f0b045021b2703486f3a93c765805f27b6b2e8","submitter":{"id":91277,"url":"http://patchwork.ozlabs.org/api/1.0/people/91277/?format=json","name":"Manivannan Sadhasivam via B4 Relay","email":"devnull+manivannan.sadhasivam.oss.qualcomm.com@kernel.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20251218-pci-dwc-suspend-rework-v2-1-5a7778c6094a@oss.qualcomm.com/mbox/","series":[{"id":485835,"url":"http://patchwork.ozlabs.org/api/1.0/series/485835/?format=json","date":"2025-12-18T12:04:51","name":"PCI: dwc: Suspend/resume rework","version":2,"mbox":"http://patchwork.ozlabs.org/series/485835/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175533/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=dxe0FiYA;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"\n <20251218-pci-dwc-suspend-rework-v2-1-5a7778c6094a@oss.qualcomm.com>","References":"\n <20251218-pci-dwc-suspend-rework-v2-0-5a7778c6094a@oss.qualcomm.com>","In-Reply-To":"\n <20251218-pci-dwc-suspend-rework-v2-0-5a7778c6094a@oss.qualcomm.com>","To":"Jingoo Han ,\n Manivannan Sadhasivam ,\n Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= ,\n Rob Herring , Bjorn Helgaas ","Cc":"linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n vincent.guittot@linaro.org, zhangsenchuan@eswincomputing.com,\n Manivannan Sadhasivam ,\n Frank Li , Shawn Lin ","X-Mailer":"b4 0.14.3","X-Developer-Signature":"v=1; a=openpgp-sha256; l=1250;\n i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id;\n bh=zzm1js4g/wb9/28LZoMBiDrVq1+JGQ8PgCaGDVkxvSs=;\n b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpQ+3laZ2TdGjXY+TPWcrdGBRDdPW7B7FcXIp27\n DNrZqWM4bmJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaUPt5QAKCRBVnxHm/pHO\n 9XTZB/4yPHL8Wjn52iy6qP+I1K8EXtv1sxI3nuQ+NSmi0q+YIqM8E04b/xCOgf6pvOLmcp+W3yV\n E7oNEl4+Eh0jGpJBUd2tueucmVGYODQDMBnNYAOAzHI7a/Q9y9QJ0Ax6czPZ4zP52tDpfpnlFp8\n h+8tuIf/L5DprSvFHPbYjxpmP/Tgrqbl8OZbo+hCVqLkWLmXZuRMXzbI0z26ywwWDdmkPANCt66\n qd9l6IWynASqsOntET8UJHhbMl5Rt6A0Qz2gf3lXW8WrUJf2zN7Giui7N5Llv7EGD0gV9M8Smcv\n PA7xqPWJ2SeJ6gL5j7O4N+fg2325R2HGbshrc3y2SIsEv70/","X-Developer-Key":"i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp;\n fpr=C668AEC3C3188E4C611465E7488550E901166008","X-Endpoint-Received":"by B4 Relay for\n manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461","X-Original-From":"Manivannan Sadhasivam\n ","Reply-To":"manivannan.sadhasivam@oss.qualcomm.com"},"content":"From: Manivannan Sadhasivam \n\nDuring system suspend, if the PCIe link is not up, then there is no need\nto broadcast PME_Turn_Off message and wait for L2/L3 transition. So skip\nthem.\n\nTested-by: Vincent Guittot \nReviewed-by: Frank Li \nReviewed-by: Shawn Lin \nSigned-off-by: Manivannan Sadhasivam \n---\n drivers/pci/controller/dwc/pcie-designware-host.c | 4 ++++\n 1 file changed, 4 insertions(+)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c\nindex 372207c33a85..43d091128ef7 100644\n--- a/drivers/pci/controller/dwc/pcie-designware-host.c\n+++ b/drivers/pci/controller/dwc/pcie-designware-host.c\n@@ -1161,6 +1161,9 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)\n \tu32 val;\n \tint ret;\n \n+\tif (!dw_pcie_link_up(pci))\n+\t\tgoto stop_link;\n+\n \t/*\n \t * If L1SS is supported, then do not put the link into L2 as some\n \t * devices such as NVMe expect low resume latency.\n@@ -1194,6 +1197,7 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)\n \t */\n \tudelay(1);\n \n+stop_link:\n \tdw_pcie_stop_link(pci);\n \tif (pci->pp.ops->deinit)\n \t\tpci->pp.ops->deinit(&pci->pp);\n","prefixes":["v2","1/2"]}