{"id":2175488,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175488/?format=json","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.0/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20251218-gicv5-host-acpi-v2-1-eec76cd1d40b@kernel.org>","date":"2025-12-18T10:14:27","name":"[v2,1/7] ACPICA: Add GICv5 MADT structures","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b6f7dc448892257526137dad75a88dc0be39a6b0","submitter":{"id":84664,"url":"http://patchwork.ozlabs.org/api/1.0/people/84664/?format=json","name":"Lorenzo Pieralisi","email":"lpieralisi@kernel.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20251218-gicv5-host-acpi-v2-1-eec76cd1d40b@kernel.org/mbox/","series":[{"id":485814,"url":"http://patchwork.ozlabs.org/api/1.0/series/485814/?format=json","date":"2025-12-18T10:14:26","name":"irqchip/gic-v5: Code first ACPI boot support","version":2,"mbox":"http://patchwork.ozlabs.org/series/485814/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175488/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=k5x6jANk;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-43274-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"k5x6jANk\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dX66h3Vk8z1y2F\n\tfor ; Thu, 18 Dec 2025 21:17:32 +1100 (AEDT)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id CA94B30B61FC\n\tfor ; Thu, 18 Dec 2025 10:15:10 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id E3EE333D510;\n\tThu, 18 Dec 2025 10:15:09 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id A799633D501;\n\tThu, 18 Dec 2025 10:15:09 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id F0317C113D0;\n\tThu, 18 Dec 2025 10:15:04 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1766052909; cv=none;\n b=EXhHnO21m7wRcL8mG/cH+YkyM21KMWVeTwCVRMqzbe8LhNmx2IdP1DK6hleKLa9zIxLvGWu3HPNdazRWTuxV9vkyk2hofsEkJ07617KM4XX2x5fJfSkb06CafZTeWDnyau47yc3cc5y4bLe4YDd/0uvEP2sVpuO2DuOSylH0fq4=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1766052909; c=relaxed/simple;\n\tbh=vnKEmMAe21QcHMZuNYI4JA27L1lMdTDSUIpCnogDK/I=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=AhqcOmdi3bgVtvkDUd4AtCzEUgKwnlpvPXU5/YHxH2A9qYIsRJex1MSYNiaLr1PCa1NAlNR0Ll00ylhkD/QahjDHi75ei24GXxOiAyuQE97Gtq8E/KtZHfQfbJYqpO+62uk7tzkFIJQHMRvrI/urHN1E6iTYADOEtzBaaOhaHyk=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=k5x6jANk; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1766052909;\n\tbh=vnKEmMAe21QcHMZuNYI4JA27L1lMdTDSUIpCnogDK/I=;\n\th=From:Date:Subject:References:In-Reply-To:To:Cc:From;\n\tb=k5x6jANk0HZCdFNmQ8ONf84TXV/hnSyODKlwPkYcldqK35T835k0zhX+1J4vW7h3x\n\t YuB87dKAHfjZqQktHnSNr4I87e8QoyWT5BOJ269qYwQLCmSCWMU2w1Q6fhpovy0gLP\n\t 4eWRN+g777w/a0xuPlSuAun1xmByvIKvT/LLFIqgow5KUjz5yV1YRNf2DWvopeDGr0\n\t P1epYRKg9q7Q1XG+lQpKfb0Yxo5vd3IJuudlbkUYwRI5n+asIIoPcWcBhAUkOjCAVe\n\t 9mfSNHPmKQKiuQvf7L3sP4dyf0ZEBcc/0nxFTgJ3I5yVKNinhOY83mAZay6hnUkWZq\n\t y4rqden517tFg==","From":"Lorenzo Pieralisi ","Date":"Thu, 18 Dec 2025 11:14:27 +0100","Subject":"[PATCH v2 1/7] ACPICA: Add GICv5 MADT structures","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20251218-gicv5-host-acpi-v2-1-eec76cd1d40b@kernel.org>","References":"<20251218-gicv5-host-acpi-v2-0-eec76cd1d40b@kernel.org>","In-Reply-To":"<20251218-gicv5-host-acpi-v2-0-eec76cd1d40b@kernel.org>","To":"\"Rafael J. Wysocki\" , Len Brown ,\n Robert Moore , Thomas Gleixner ,\n Hanjun Guo , Sudeep Holla ,\n Marc Zyngier , Bjorn Helgaas ","Cc":"linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev,\n linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n linux-pci@vger.kernel.org, Lorenzo Pieralisi ,\n Jose Marinho ","X-Mailer":"b4 0.14.3"},"content":"From: Jose Marinho \n\nThe GICv5 adds the following MADT structures:\n- IRS\n- ITS Config Frame\n- ITS Translate Frame\n\nThe ACPI spec ECR is at https://github.com/tianocore/edk2/issues/11148\n\nLink: https://github.com/acpica/acpica/commit/69cca52d\nSigned-off-by: Jose Marinho \nSigned-off-by: Bob Moore \nSigned-off-by: Lorenzo Pieralisi \n---\n include/acpi/actbl2.h | 49 +++++++++++++++++++++++++++++++++++++++++++++----\n 1 file changed, 45 insertions(+), 4 deletions(-)","diff":"diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h\nindex f726bce3eb84..fdabc6c64a9c 100644\n--- a/include/acpi/actbl2.h\n+++ b/include/acpi/actbl2.h\n@@ -1167,7 +1167,10 @@ enum acpi_madt_type {\n \tACPI_MADT_TYPE_IMSIC = 25,\n \tACPI_MADT_TYPE_APLIC = 26,\n \tACPI_MADT_TYPE_PLIC = 27,\n-\tACPI_MADT_TYPE_RESERVED = 28,\t/* 28 to 0x7F are reserved */\n+\tACPI_MADT_TYPE_GICV5_IRS = 28,\n+\tACPI_MADT_TYPE_GICV5_ITS = 29,\n+\tACPI_MADT_TYPE_GICV5_ITS_TRANSLATE = 30,\n+\tACPI_MADT_TYPE_RESERVED = 31,\t/* 31 to 0x7F are reserved */\n \tACPI_MADT_TYPE_OEM_RESERVED = 0x80\t/* 0x80 to 0xFF are reserved for OEM use */\n };\n \n@@ -1289,7 +1292,7 @@ struct acpi_madt_local_x2apic_nmi {\n \tu8 reserved[3];\t\t/* reserved - must be zero */\n };\n \n-/* 11: Generic interrupt - GICC (ACPI 5.0 + ACPI 6.0 + ACPI 6.3 + ACPI 6.5 changes) */\n+/* 11: Generic interrupt - GICC (ACPI 5.0 + ACPI 6.0 + ACPI 6.3 + ACPI 6.5 + ACPI 6.7 changes) */\n \n struct acpi_madt_generic_interrupt {\n \tstruct acpi_subtable_header header;\n@@ -1310,6 +1313,8 @@ struct acpi_madt_generic_interrupt {\n \tu8 reserved2[1];\n \tu16 spe_interrupt;\t/* ACPI 6.3 */\n \tu16 trbe_interrupt;\t/* ACPI 6.5 */\n+\tu16 iaffid;\t\t/* ACPI 6.7 */\n+\tu32 irs_id;\n };\n \n /* Masks for Flags field above */\n@@ -1332,7 +1337,7 @@ struct acpi_madt_generic_distributor {\n \tu8 reserved2[3];\t/* reserved - must be zero */\n };\n \n-/* Values for Version field above */\n+/* Values for Version field above and Version field in acpi_madt_gicv5_irs */\n \n enum acpi_madt_gic_version {\n \tACPI_MADT_GIC_VERSION_NONE = 0,\n@@ -1340,7 +1345,8 @@ enum acpi_madt_gic_version {\n \tACPI_MADT_GIC_VERSION_V2 = 2,\n \tACPI_MADT_GIC_VERSION_V3 = 3,\n \tACPI_MADT_GIC_VERSION_V4 = 4,\n-\tACPI_MADT_GIC_VERSION_RESERVED = 5\t/* 5 and greater are reserved */\n+\tACPI_MADT_GIC_VERSION_V5 = 5,\n+\tACPI_MADT_GIC_VERSION_RESERVED = 6\t/* 6 and greater are reserved */\n };\n \n /* 13: Generic MSI Frame (ACPI 5.1) */\n@@ -1611,6 +1617,41 @@ struct acpi_madt_plic {\n \tu32 gsi_base;\n };\n \n+/* 28: Arm GICv5 IRS (ACPI 6.7) */\n+struct acpi_madt_gicv5_irs {\n+\tstruct acpi_subtable_header header;\n+\tu8 version;\n+\tu8 reserved;\n+\tu32 irs_id;\n+\tu32 flags;\n+\tu32 reserved2;\n+\tu64 config_base_address;\n+\tu64 setlpi_base_address;\n+};\n+\n+#define ACPI_MADT_IRS_NON_COHERENT (1)\n+\n+/* 29: Arm GICv5 ITS Config Frame (ACPI 6.7) */\n+struct acpi_madt_gicv5_translator {\n+\tstruct acpi_subtable_header header;\n+\tu8 flags;\n+\tu8 reserved;\t\t/* reserved - must be zero */\n+\tu32 translator_id;\n+\tu64 base_address;\n+};\n+\n+#define ACPI_MADT_GICV5_ITS_NON_COHERENT (1)\n+\n+/* 30: Arm GICv5 ITS Translate Frame (ACPI 6.7) */\n+struct acpi_madt_gicv5_translate_frame {\n+\tstruct acpi_subtable_header header;\n+\tu16 reserved;\t\t/* reserved - must be zero */\n+\tu32 linked_translator_id;\n+\tu32 translate_frame_id;\n+\tu32 reserved2;\n+\tu64 base_address;\n+};\n+\n /* 80: OEM data */\n \n struct acpi_madt_oem_data {\n","prefixes":["v2","1/7"]}