{"id":2175423,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175423/?format=json","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.0/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20251218061557.1999367-3-varadarajan.narayanan@oss.qualcomm.com>","date":"2025-12-18T06:15:53","name":"[RESEND,v2,2/6] phy: Add IPQ9574 support to Qualcomm QUSB2 phy","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"32deaac35d10e07f7e4db640525c6b853df13a99","submitter":{"id":92283,"url":"http://patchwork.ozlabs.org/api/1.0/people/92283/?format=json","name":"Varadarajan Narayanan","email":"varadarajan.narayanan@oss.qualcomm.com"},"delegate":{"id":151538,"url":"http://patchwork.ozlabs.org/api/1.0/users/151538/?format=json","username":"kcxt","first_name":"Casey","last_name":"Connolly","email":"casey.connolly@linaro.org"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20251218061557.1999367-3-varadarajan.narayanan@oss.qualcomm.com/mbox/","series":[{"id":485788,"url":"http://patchwork.ozlabs.org/api/1.0/series/485788/?format=json","date":"2025-12-18T06:15:51","name":"Enable fastboot support for IPQ9574 based boards","version":2,"mbox":"http://patchwork.ozlabs.org/series/485788/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175423/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=Jr9fzWoG;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=PmNVPhl1;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"Jr9fzWoG\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"PmNVPhl1\";\n\tdkim-atps=neutral","phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com","phobos.denx.de; spf=pass\n smtp.mailfrom=varadarajan.narayanan@oss.qualcomm.com"],"Received":["from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dX0mh3Pdlz1y2F\n\tfor ; Thu, 18 Dec 2025 17:16:36 +1100 (AEDT)","from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 1B26883C91;\n\tThu, 18 Dec 2025 07:16:22 +0100 (CET)","by phobos.denx.de (Postfix, from userid 109)\n id 6053283B55; Thu, 18 Dec 2025 07:16:21 +0100 (CET)","from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 3C0D183C91\n for ; Thu, 18 Dec 2025 07:16:19 +0100 (CET)","from pps.filterd (m0279871.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 5BI1YYhJ680548\n for ; Thu, 18 Dec 2025 06:16:17 GMT","from mail-pg1-f198.google.com (mail-pg1-f198.google.com\n [209.85.215.198])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b45bhh2ph-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for ; Thu, 18 Dec 2025 06:16:17 +0000 (GMT)","by mail-pg1-f198.google.com with SMTP id\n 41be03b00d2f7-c1d27c65670so343744a12.1\n for ; Wed, 17 Dec 2025 22:16:17 -0800 (PST)","from hu-varada-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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AGHT+IG63k1soPYvPH9NU+4hYfodShrXpnWcQ8x8HZNCaMuwataV5BNmm/LhQ+HPpW6bvlT9gXGrWA==","From":"Varadarajan Narayanan ","To":"trini@konsulko.com, casey.connolly@linaro.org, neil.armstrong@linaro.org,\n sumit.garg@kernel.org, peng.fan@nxp.com, jh80.chung@samsung.com,\n lukma@denx.de, varadarajan.narayanan@oss.qualcomm.com,\n marek.vasut+renesas@mailbox.org, michal.simek@amd.com,\n alexeymin@postmarketos.org, u-boot@lists.denx.de, u-boot-qcom@groups.io","Subject":"[RESEND v2 2/6] phy: Add IPQ9574 support to Qualcomm QUSB2 phy","Date":"Thu, 18 Dec 2025 11:45:53 +0530","Message-Id":"<20251218061557.1999367-3-varadarajan.narayanan@oss.qualcomm.com>","X-Mailer":"git-send-email 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","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Imported from Linux driver.\n\nSigned-off-by: Varadarajan Narayanan \n---\n drivers/phy/qcom/phy-qcom-qusb2.c | 42 +++++++++++++++++++++++++++++++\n 1 file changed, 42 insertions(+)","diff":"diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c b/drivers/phy/qcom/phy-qcom-qusb2.c\nindex d98f6108e69..df82f2a99da 100644\n--- a/drivers/phy/qcom/phy-qcom-qusb2.c\n+++ b/drivers/phy/qcom/phy-qcom-qusb2.c\n@@ -152,6 +152,22 @@ enum qusb2phy_reg_layout {\n \t\t.offset = o, .val = v, .in_layout = 1, \\\n \t}\n \n+static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = {\n+\tQUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14),\n+\tQUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xF8),\n+\tQUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xB3),\n+\tQUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),\n+\tQUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xC0),\n+\tQUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),\n+\tQUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),\n+\tQUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),\n+\tQUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00),\n+\tQUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),\n+\tQUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),\n+\tQUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80),\n+\tQUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F),\n+};\n+\n static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = {\n \tQUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),\n \tQUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53),\n@@ -168,6 +184,19 @@ static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = {\n \tQUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),\n };\n \n+static const unsigned int ipq6018_regs_layout[] = {\n+\t[QUSB2PHY_PLL_STATUS]\t\t= 0x38,\n+\t[QUSB2PHY_PORT_TUNE1]\t\t= 0x80,\n+\t[QUSB2PHY_PORT_TUNE2]\t\t= 0x84,\n+\t[QUSB2PHY_PORT_TUNE3]\t\t= 0x88,\n+\t[QUSB2PHY_PORT_TUNE4]\t\t= 0x8C,\n+\t[QUSB2PHY_PORT_TUNE5]\t\t= 0x90,\n+\t[QUSB2PHY_PORT_TEST1]\t\t= 0x98,\n+\t[QUSB2PHY_PORT_TEST2]\t\t= 0x9C,\n+\t[QUSB2PHY_PORT_POWERDOWN]\t= 0xB4,\n+\t[QUSB2PHY_INTR_CTRL]\t\t= 0xBC,\n+};\n+\n static const unsigned int sm6115_regs_layout[] = {\n \t[QUSB2PHY_PLL_STATUS] = 0x38,\t [QUSB2PHY_PORT_TUNE1] = 0x80,\n \t[QUSB2PHY_PORT_TUNE2] = 0x84,\t [QUSB2PHY_PORT_TUNE3] = 0x88,\n@@ -224,6 +253,17 @@ static const unsigned int qusb2_v2_regs_layout[] = {\n \t[QUSB2PHY_INTR_CTRL] = 0x230,\n };\n \n+static const struct qusb2_phy_cfg ipq6018_phy_cfg = {\n+\t.tbl = ipq6018_init_tbl,\n+\t.tbl_num = ARRAY_SIZE(ipq6018_init_tbl),\n+\t.regs = ipq6018_regs_layout,\n+\n+\t.disable_ctrl = POWER_DOWN,\n+\t.mask_core_ready = PLL_LOCKED,\n+\t/* autoresume not used */\n+\t.autoresume_en = BIT(0),\n+};\n+\n static const struct qusb2_phy_cfg sm6115_phy_cfg = {\n \t.tbl = sm6115_init_tbl,\n \t.tbl_num = ARRAY_SIZE(sm6115_init_tbl),\n@@ -455,6 +495,8 @@ static const struct udevice_id qusb2phy_ids[] = {\n \t .data = (ulong)&sm6115_phy_cfg },\n \t{ .compatible = \"qcom,sdm660-qusb2-phy\",\n \t .data = (ulong)&sdm660_phy_cfg },\n+\t{ .compatible = \"qcom,ipq9574-qusb2-phy\",\n+\t .data = (ulong)&ipq6018_phy_cfg },\n \t{ .compatible = \"qcom,sm6115-qusb2-phy\",\n \t .data = (ulong)&sm6115_phy_cfg },\n \t{ .compatible = \"qcom,qusb2-v2-phy\", .data = (ulong)&qusb2_v2_phy_cfg },\n","prefixes":["RESEND","v2","2/6"]}