{"id":2175422,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175422/?format=json","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.0/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20251218061557.1999367-2-varadarajan.narayanan@oss.qualcomm.com>","date":"2025-12-18T06:15:52","name":"[RESEND,v2,1/6] clk/qcom: Add USB related clocks for IPQ9574","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"57b7780056633d614f81f145d56120ad66586f60","submitter":{"id":92283,"url":"http://patchwork.ozlabs.org/api/1.0/people/92283/?format=json","name":"Varadarajan Narayanan","email":"varadarajan.narayanan@oss.qualcomm.com"},"delegate":{"id":151538,"url":"http://patchwork.ozlabs.org/api/1.0/users/151538/?format=json","username":"kcxt","first_name":"Casey","last_name":"Connolly","email":"casey.connolly@linaro.org"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20251218061557.1999367-2-varadarajan.narayanan@oss.qualcomm.com/mbox/","series":[{"id":485788,"url":"http://patchwork.ozlabs.org/api/1.0/series/485788/?format=json","date":"2025-12-18T06:15:51","name":"Enable fastboot support for IPQ9574 based boards","version":2,"mbox":"http://patchwork.ozlabs.org/series/485788/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175422/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=HBS/dSTC;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Acs5jc4z;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"HBS/dSTC\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"Acs5jc4z\";\n\tdkim-atps=neutral","phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com","phobos.denx.de; spf=pass\n smtp.mailfrom=varadarajan.narayanan@oss.qualcomm.com"],"Received":["from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dX0mW0lctz1y3k\n\tfor ; Thu, 18 Dec 2025 17:16:27 +1100 (AEDT)","from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id D3C0B83C54;\n\tThu, 18 Dec 2025 07:16:18 +0100 (CET)","by phobos.denx.de (Postfix, from userid 109)\n id 9EB6E83C8C; Thu, 18 Dec 2025 07:16:17 +0100 (CET)","from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com\n [205.220.168.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 5815D83B55\n for ; Thu, 18 Dec 2025 07:16:15 +0100 (CET)","from pps.filterd (m0279866.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 5BI1YiO53717103\n for ; Thu, 18 Dec 2025 06:16:13 GMT","from mail-pg1-f199.google.com (mail-pg1-f199.google.com\n [209.85.215.199])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4b40n79yb4-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for ; Thu, 18 Dec 2025 06:16:13 +0000 (GMT)","by mail-pg1-f199.google.com with SMTP id\n 41be03b00d2f7-b993eb2701bso353573a12.0\n for ; Wed, 17 Dec 2025 22:16:13 -0800 (PST)","from hu-varada-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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AGHT+IHRAkACv8qlzcqCARPxEOj6QTDQD1cRXrmSQOEJyTy0NoHogxE/72Q0B4SptyWR3tlInsDwmw==","From":"Varadarajan Narayanan ","To":"trini@konsulko.com, casey.connolly@linaro.org, neil.armstrong@linaro.org,\n sumit.garg@kernel.org, peng.fan@nxp.com, jh80.chung@samsung.com,\n lukma@denx.de, varadarajan.narayanan@oss.qualcomm.com,\n marek.vasut+renesas@mailbox.org, michal.simek@amd.com,\n alexeymin@postmarketos.org, u-boot@lists.denx.de, u-boot-qcom@groups.io","Subject":"[RESEND v2 1/6] clk/qcom: Add USB related clocks for IPQ9574","Date":"Thu, 18 Dec 2025 11:45:52 +0530","Message-Id":"<20251218061557.1999367-2-varadarajan.narayanan@oss.qualcomm.com>","X-Mailer":"git-send-email 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","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Add the USB controller and phy related clocks.\n\nSigned-off-by: Varadarajan Narayanan \n---\n drivers/clk/qcom/clock-ipq9574.c | 28 ++++++++++++++++++++++++++++\n 1 file changed, 28 insertions(+)","diff":"diff --git a/drivers/clk/qcom/clock-ipq9574.c b/drivers/clk/qcom/clock-ipq9574.c\nindex b0af4036059..1f5146b29a1 100644\n--- a/drivers/clk/qcom/clock-ipq9574.c\n+++ b/drivers/clk/qcom/clock-ipq9574.c\n@@ -25,6 +25,9 @@\n #define GCC_SDCC1_AHB_CBCR\t\t\t0x33034\n #define GCC_SDCC1_APPS_CMD_RCGR\t\t\t0x33004\n #define GCC_SDCC1_ICE_CORE_CBCR\t\t\t0x33030\n+#define GCC_USB0_MASTER_CMD_RCGR\t\t0x2c004\n+#define GCC_USB0_MOCK_UTMI_CMD_RCGR\t\t0x2c02c\n+#define GCC_USB0_AUX_CMD_RCGR\t\t\t0x2C018\n \n static ulong ipq9574_set_rate(struct clk *clk, ulong rate)\n {\n@@ -39,6 +42,17 @@ static ulong ipq9574_set_rate(struct clk *clk, ulong rate)\n \t\tclk_rcg_set_rate_mnd(priv->base, GCC_SDCC1_APPS_CMD_RCGR,\n \t\t\t\t 11, 0, 0, CFG_CLK_SRC_GPLL2, 16);\n \t\treturn rate;\n+\tcase GCC_USB0_MASTER_CLK:\n+\t\tclk_rcg_set_rate(priv->base, GCC_USB0_MASTER_CMD_RCGR,\n+\t\t\t\t 4, CFG_CLK_SRC_GPLL0);\n+\t\treturn rate;\n+\tcase GCC_USB0_MOCK_UTMI_CLK:\n+\t\tclk_rcg_set_rate_mnd(priv->base, GCC_USB0_MOCK_UTMI_CMD_RCGR,\n+\t\t\t\t 0, 0, 0, CFG_CLK_SRC_CXO, 8);\n+\t\treturn rate;\n+\tcase GCC_USB0_AUX_CLK:\n+\t\tclk_rcg_set_rate_mnd(priv->base, GCC_USB0_AUX_CMD_RCGR, 0, 0, 0,\n+\t\t\t\t CFG_CLK_SRC_CXO, 8);\n \tdefault:\n \t\treturn -EINVAL;\n \t}\n@@ -50,6 +64,14 @@ static const struct gate_clk ipq9574_clks[] = {\n \tGATE_CLK(GCC_SDCC1_AHB_CLK,\t\t0x33034, 0x00000001),\n \tGATE_CLK(GCC_SDCC1_APPS_CLK,\t\t0x3302C, 0x00000001),\n \tGATE_CLK(GCC_SDCC1_ICE_CORE_CLK,\t0x33030, 0x00000001),\n+\tGATE_CLK(GCC_SNOC_USB_CLK,\t\t0x2e058, 0x00000001),\n+\tGATE_CLK(GCC_USB0_MASTER_CLK,\t\t0x2c044, 0x00000001),\n+\tGATE_CLK(GCC_ANOC_USB_AXI_CLK,\t\t0x2e084, 0x00000001),\n+\tGATE_CLK(GCC_USB0_SLEEP_CLK,\t\t0x2c058, 0x00000001),\n+\tGATE_CLK(GCC_USB0_MOCK_UTMI_CLK,\t0x2c04c, 0x00000001),\n+\tGATE_CLK(GCC_USB0_PHY_CFG_AHB_CLK,\t0x2c05c, 0x00000001),\n+\tGATE_CLK(GCC_USB0_AUX_CLK,\t\t0x2c048, 0x00000001),\n+\tGATE_CLK(GCC_USB0_PIPE_CLK,\t\t0x2c054, 0x00000001),\n };\n \n static int ipq9574_enable(struct clk *clk)\n@@ -67,6 +89,10 @@ static int ipq9574_enable(struct clk *clk)\n }\n \n static const struct qcom_reset_map ipq9574_gcc_resets[] = {\n+\t[GCC_USB_BCR] = { 0x2c000 },\n+\t[GCC_QUSB2_0_PHY_BCR] = { 0x2c068 },\n+\t[GCC_USB0_PHY_BCR] = {0x2c06c, 0},\n+\t[GCC_USB3PHY_0_PHY_BCR] = {0x2c070, 0},\n \t[GCC_SDCC_BCR] = { 0x33000 },\n };\n \n@@ -75,6 +101,8 @@ static struct msm_clk_data ipq9574_gcc_data = {\n \t.num_resets = ARRAY_SIZE(ipq9574_gcc_resets),\n \t.enable = ipq9574_enable,\n \t.set_rate = ipq9574_set_rate,\n+\t.clks = ipq9574_clks,\n+\t.num_clks = ARRAY_SIZE(ipq9574_clks),\n };\n \n static const struct udevice_id gcc_ipq9574_of_match[] = {\n","prefixes":["RESEND","v2","1/6"]}