{"id":2175381,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175381/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20251217212018.93320-7-gustavo.romero@linaro.org>","date":"2025-12-17T21:20:18","name":"[v2,6/6] system/physmem: Use cpu_address_space_init to set cpu->num_ases","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"91fde6476682f710e2ff3970dd8da25d67dacbf1","submitter":{"id":82513,"url":"http://patchwork.ozlabs.org/api/1.0/people/82513/?format=json","name":"Gustavo Romero","email":"gustavo.romero@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20251217212018.93320-7-gustavo.romero@linaro.org/mbox/","series":[{"id":485770,"url":"http://patchwork.ozlabs.org/api/1.0/series/485770/?format=json","date":"2025-12-17T21:20:12","name":"system/physmem: Enhance the Address Space API","version":2,"mbox":"http://patchwork.ozlabs.org/series/485770/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175381/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=blbz8Fkq;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dWmvp4QgLz1xpw\n\tfor ; Thu, 18 Dec 2025 08:21:58 +1100 (AEDT)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1vVyxQ-0000C1-VB; Wed, 17 Dec 2025 16:21:16 -0500","from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1vVyxM-00007M-MO\n for qemu-devel@nongnu.org; Wed, 17 Dec 2025 16:21:12 -0500","from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1vVyxL-0004dq-0j\n for qemu-devel@nongnu.org; Wed, 17 Dec 2025 16:21:12 -0500","by mail-pf1-x432.google.com with SMTP id\n d2e1a72fcca58-7acd9a03ba9so7097583b3a.1\n for ; Wed, 17 Dec 2025 13:21:10 -0800 (PST)","from gromero0.. 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helo=mail-pf1-x432.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Use the new cpu_address_space_init function to set the total number of\nASes in a CPU instead of directly setting it via cpu->num_ases.\n\nSigned-off-by: Gustavo Romero \n---\n system/cpus.c | 4 ++--\n target/arm/cpu.c | 10 +---------\n target/i386/kvm/kvm-cpu.c | 3 ++-\n target/i386/tcg/system/tcg-cpu.c | 2 +-\n 4 files changed, 6 insertions(+), 13 deletions(-)","diff":"diff --git a/system/cpus.c b/system/cpus.c\nindex fa9deafa29..54be6a3faf 100644\n--- a/system/cpus.c\n+++ b/system/cpus.c\n@@ -718,8 +718,8 @@ void qemu_init_vcpu(CPUState *cpu)\n /* If the target cpu hasn't set up any address spaces itself,\n * give it the default one.\n */\n- cpu->num_ases = 1;\n- cpu_address_space_add(cpu, 0, \"cpu-memory\", cpu->memory);\n+ cpu_address_space_init(cpu, 1 /* Number of ASes */);\n+ cpu_address_space_add(cpu, 0 /* AS index */, \"cpu-memory\", cpu->memory);\n }\n \n /* accelerators all implement the AccelOpsClass */\ndiff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex 1902c510f9..67ad6f0a6e 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -2148,15 +2148,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)\n unsigned int smp_cpus = ms->smp.cpus;\n bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY);\n \n- /*\n- * We must set cs->num_ases to the final value before\n- * the first call to cpu_address_space_init.\n- */\n- if (cpu->tag_memory != NULL) {\n- cs->num_ases = 3 + has_secure;\n- } else {\n- cs->num_ases = 1 + has_secure;\n- }\n+ cpu_address_space_init(cs, ARMASIdx_MAX);\n \n cpu_address_space_add(cs, ARMASIdx_NS, \"cpu-memory\", cs->memory);\n \ndiff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c\nindex a6d94d0620..dbb04ef051 100644\n--- a/target/i386/kvm/kvm-cpu.c\n+++ b/target/i386/kvm/kvm-cpu.c\n@@ -92,13 +92,14 @@ static bool kvm_cpu_realizefn(CPUState *cs, Error **errp)\n kvm_set_guest_phys_bits(cs);\n }\n \n+ cpu_address_space_init(cs, X86ASIdx_MAX);\n+\n /*\n * When SMM is enabled, there is 2 address spaces. Otherwise only 1.\n *\n * Only initialize address space 0 here, the second one for SMM is\n * initialized at register_smram_listener() after machine init done.\n */\n- cs->num_ases = x86_machine_is_smm_enabled(X86_MACHINE(current_machine)) ? 2 : 1;\n cpu_address_space_add(cs, X86ASIdx_MEM, \"cpu-memory\", cs->memory);\n \n return true;\ndiff --git a/target/i386/tcg/system/tcg-cpu.c b/target/i386/tcg/system/tcg-cpu.c\nindex 231a4bdf55..ab72c5ff7b 100644\n--- a/target/i386/tcg/system/tcg-cpu.c\n+++ b/target/i386/tcg/system/tcg-cpu.c\n@@ -73,7 +73,7 @@ bool tcg_cpu_realizefn(CPUState *cs, Error **errp)\n memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);\n memory_region_set_enabled(cpu->cpu_as_mem, true);\n \n- cs->num_ases = 2;\n+ cpu_address_space_init(cs, X86ASIdx_MAX);\n cpu_address_space_add(cs, X86ASIdx_MEM, \"cpu-memory\", cs->memory);\n cpu_address_space_add(cs, X86ASIdx_SMM, \"cpu-smm\", cpu->cpu_as_root);\n \n","prefixes":["v2","6/6"]}