{"id":2175315,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175315/?format=json","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.0/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20251217190018.487429-5-rdapp@ventanamicro.com>","date":"2025-12-17T19:00:18","name":"[v3,4/4] RISC-V: Generic vec_extract via subreg.","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"9261b9716281d49e0ad16ca5c2ed986d9a843b00","submitter":{"id":86205,"url":"http://patchwork.ozlabs.org/api/1.0/people/86205/?format=json","name":"Robin Dapp","email":"rdapp.gcc@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/20251217190018.487429-5-rdapp@ventanamicro.com/mbox/","series":[{"id":485748,"url":"http://patchwork.ozlabs.org/api/1.0/series/485748/?format=json","date":"2025-12-17T19:00:18","name":"VLS-related stuff.","version":3,"mbox":"http://patchwork.ozlabs.org/series/485748/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175315/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=RK4IPAHb;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)","sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=RK4IPAHb","sourceware.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com","sourceware.org; spf=pass smtp.mailfrom=gmail.com","server2.sourceware.org;\n arc=none smtp.remote-ip=209.85.218.46"],"Received":["from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dWjng0w6wz1xty\n\tfor ; Thu, 18 Dec 2025 06:01:27 +1100 (AEDT)","from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 135394BA2E2C\n\tfor ; Wed, 17 Dec 2025 19:01:25 +0000 (GMT)","from mail-ej1-f46.google.com (mail-ej1-f46.google.com\n [209.85.218.46])\n by sourceware.org (Postfix) with ESMTPS id BD73D4BA2E28\n for ; Wed, 17 Dec 2025 19:00:26 +0000 (GMT)","by mail-ej1-f46.google.com with SMTP id\n a640c23a62f3a-b7633027cb2so1097162566b.1\n for ; Wed, 17 Dec 2025 11:00:26 -0800 (PST)","from x1c10.dc1.ventanamicro.com\n (ip-149-172-150-237.um42.pools.vodafone-ip.de. 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In particular we don't extract from\npseudo-VLA modes that are actually VLS modes (just VLA modes in name).\n\nRather than add even more mode combinations to vec_extract, this patch\nuses a dynamic approach in legitimize_move. At that point we can just check\nif the mode sizes make sense and then emit the same code as before.\n\nThis is not the ideal solution as the middle-end and the vectorizer in\nparticular queries the vec_extract optab for support and won't emit\ncertain code sequences if it's not present (e.g. in VMAT_STRIDED_SLP\nor when trying intermediate-sized vectors in a chain).\nFor simple BIT_FIELD_REFs it works, though.\n\ngcc/ChangeLog:\n\n\t* config/riscv/riscv-v.cc (expand_vector_subreg_extract): New\n\tfunction that checks for and performs \"vector extracts\".\n\t(legitimize_move): Call new function.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/rvv/autovec/subreg-extract.c: New test.\n---\n gcc/config/riscv/riscv-v.cc | 88 +++++++++++++++++++\n .../riscv/rvv/autovec/subreg-extract.c | 19 ++++\n 2 files changed, 107 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/subreg-extract.c","diff":"diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc\nindex e519211d691..321b5172783 100644\n--- a/gcc/config/riscv/riscv-v.cc\n+++ b/gcc/config/riscv/riscv-v.cc\n@@ -1880,6 +1880,76 @@ get_frm_mode (rtx operand)\n gcc_unreachable ();\n }\n \n+/* Expand vector extraction from a SUBREG source using slidedown.\n+ Handles patterns like (subreg:V4DI (reg:V8DI) 32) by emitting\n+ a slidedown instruction when extracting non-low parts.\n+ Return true if the move was handled and emitted. */\n+static bool\n+expand_vector_subreg_extract (rtx dest, rtx src)\n+{\n+ gcc_assert (SUBREG_P (src) && REG_P (SUBREG_REG (src)));\n+\n+ machine_mode mode = GET_MODE (dest);\n+ machine_mode inner_mode = GET_MODE (SUBREG_REG (src));\n+\n+ gcc_assert (VECTOR_MODE_P (mode));\n+ gcc_assert (VECTOR_MODE_P (inner_mode));\n+\n+ poly_uint16 outer_size = GET_MODE_BITSIZE (mode);\n+ poly_uint16 inner_size = GET_MODE_BITSIZE (inner_mode);\n+\n+ poly_uint16 factor;\n+ if (riscv_tuple_mode_p (inner_mode)\n+ || !multiple_p (inner_size, outer_size, &factor)\n+ || !factor.is_constant ()\n+ || !pow2p_hwi (factor.to_constant ())\n+ || factor.to_constant () <= 1)\n+ return false;\n+\n+ enum vlmul_type lmul = get_vlmul (mode);\n+ enum vlmul_type inner_lmul = get_vlmul (inner_mode);\n+\n+ /* These are just \"renames\". */\n+ if ((inner_lmul == LMUL_2 || inner_lmul == LMUL_4 || inner_lmul == LMUL_8)\n+ && (lmul == LMUL_1 || lmul == LMUL_2 || lmul == LMUL_4))\n+ return false;\n+\n+ poly_uint64 outer_nunits = GET_MODE_NUNITS (mode);\n+ poly_uint64 subreg_byte = SUBREG_BYTE (src);\n+\n+ /* Calculate which part we're extracting (0 for low half, 1 for\n+ higher half/quarter, etc.) */\n+ uint64_t part;\n+ if (!exact_div (subreg_byte * BITS_PER_UNIT, outer_size).is_constant (&part))\n+ return false;\n+\n+ rtx inner_reg = SUBREG_REG (src);\n+ rtx tmp_out = gen_reg_rtx (mode);\n+\n+ if (part == 0)\n+ {\n+ /* Emit a direct reg-reg set here instead of emit_move_insn as that\n+\t would trigger another legitimize_move. */\n+ emit_insn (gen_rtx_SET (tmp_out, gen_lowpart (mode, inner_reg)));\n+ }\n+ else\n+ {\n+ /* Extracting a non-zero part means we need to slide down. */\n+ poly_uint64 slide_count = part * outer_nunits;\n+\n+ rtx tmp = gen_reg_rtx (inner_mode);\n+ rtx ops[] = {tmp, inner_reg, gen_int_mode (slide_count, Pmode)};\n+ insn_code icode = code_for_pred_slide (UNSPEC_VSLIDEDOWN, inner_mode);\n+ emit_vlmax_insn (icode, BINARY_OP, ops);\n+\n+ /* Extract the low part after sliding. */\n+ emit_insn (gen_rtx_SET (tmp_out, gen_lowpart (mode, tmp)));\n+ }\n+\n+ emit_move_insn (dest, tmp_out);\n+ return true;\n+}\n+\n /* Expand a pre-RA RVV data move from SRC to DEST.\n It expands move for RVV fractional vector modes.\n Return true if the move as already been emitted. */\n@@ -1894,6 +1964,24 @@ legitimize_move (rtx dest, rtx *srcp)\n return true;\n }\n \n+ /* The canonical way of extracting vectors from vectors is the vec_extract\n+ optab with appropriate source and dest modes. This is rather a VLS style\n+ approach, though as we would need to enumerate all dest modes that are\n+ half, quarter, etc. the size of the source. It becomes particularly\n+ cumbersome if we have a mix of VLA and VLS, i.e. extracting a smaller\n+ VLS vector from a \"VLA\" vector. Therefore we recognize patterns like\n+ (set reg:V4DI\n+\t (subreg:V4DI (reg:V8DI) offset))\n+ and transform them into vector slidedowns. */\n+ if (SUBREG_P (src) && REG_P (SUBREG_REG (src))\n+ && VECTOR_MODE_P (GET_MODE (SUBREG_REG (src)))\n+ && VECTOR_MODE_P (mode)\n+ && !lra_in_progress)\n+ {\n+ if (expand_vector_subreg_extract (dest, src))\n+\treturn true;\n+ }\n+\n if (riscv_vls_mode_p (mode))\n {\n if (GET_MODE_NUNITS (mode).to_constant () <= 31)\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/subreg-extract.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/subreg-extract.c\nnew file mode 100644\nindex 00000000000..a2b568a0ee7\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/subreg-extract.c\n@@ -0,0 +1,19 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O3 -march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -fno-vect-cost-model\" } */\n+\n+int a[35] = { 1, 1, 3 };\n+\n+void\n+foo ()\n+{\n+ for (int b = 4; b >= 0; b--)\n+ {\n+ int tem = a[b * 5 + 3 + 1];\n+ a[b * 5 + 3] = tem;\n+ a[b * 5 + 2] = tem;\n+ a[b * 5 + 1] = tem;\n+ a[b * 5 + 0] = tem;\n+ }\n+}\n+\n+/* { dg-final { scan-assembler-times \"vslidedown\" 2 } } */\n","prefixes":["v3","4/4"]}