{"id":2175243,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175243/?format=json","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.0/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20251217-dt-bindings-pci-qcom-v2-12-873721599754@oss.qualcomm.com>","date":"2025-12-17T16:19:18","name":"[v2,12/12] dt-bindings: PCI: qcom,pcie-apq8084: Move APQ8084 to dedicated schema","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"7c633b7d4863bdbce4f731e2518808cc63457c21","submitter":{"id":92171,"url":"http://patchwork.ozlabs.org/api/1.0/people/92171/?format=json","name":"Krzysztof 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=?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= ,\n Manivannan Sadhasivam , Rob Herring ,\n Krzysztof Kozlowski , Conor Dooley ,\n Bjorn Andersson ","Cc":"linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n Krzysztof Kozlowski ","X-Mailer":"b4 0.14.3","X-Developer-Signature":"v=1; a=openpgp-sha256; l=9690;\n i=krzysztof.kozlowski@oss.qualcomm.com; h=from:subject:message-id;\n bh=NnZyOyFe4FnWrR22Z6ZQaG8VqxTtc1lzACMmhkeCFlY=;\n b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBpQtgGGmH7Vf9cEL7vLe8i382DU4vNF3YU/4eul\n S53gtblGHyJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaULYBgAKCRDBN2bmhouD\n 1zguEACLbarrFplIOVoJMOleMAjkKWo3ji26Kl3m5SewnOLsV058qiJw7ZCuvRv6P4Wv1mOJdWH\n la9SkR5f7vveVEr2zOCM89p1uGRa7vodej1XRTek02GFl/AJet4HvumH/F93oZMopyJ+xKCgswY\n /2pYBzNu039phHifF7ZTvZKOxNR0nOlGF6wNPd+UlTXxmlW043aagGdwQBzekiG/vXOfhK423pe\n FgimePO2l1x24uyCwXT6PuxmYa+5kXz7Ygw/bKi76d3q4Igwpj1Iv3XYF7zQTxklsnz8sIINXsG\n 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authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512170128"},"content":"Move APQ8084 PCIe devices from qcom,pcie.yaml binding to a dedicated\nfile to make reviewing and maintenance easier.\n\nNew schema is equivalent to the old one with few changes:\n - Adding a required compatible, which is actually redundant.\n - Drop the really obvious comments next to clock/reg/reset-names items.\n\nAfter moving the qcom,pcie.yaml becames empty thus can be entirely\nremoved.\n\nReviewed-by: Rob Herring (Arm) \nSigned-off-by: Krzysztof Kozlowski \n---\n .../devicetree/bindings/pci/qcom,pcie-apq8084.yaml | 109 ++++++++++\n .../devicetree/bindings/pci/qcom,pcie.yaml | 227 ---------------------\n 2 files changed, 109 insertions(+), 227 deletions(-)","diff":"diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-apq8084.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-apq8084.yaml\nnew file mode 100644\nindex 000000000000..a6403a3de076\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-apq8084.yaml\n@@ -0,0 +1,109 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pci/qcom,pcie-apq8084.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm APQ8084 PCI Express Root Complex\n+\n+maintainers:\n+ - Bjorn Andersson \n+ - Manivannan Sadhasivam \n+\n+properties:\n+ compatible:\n+ enum:\n+ - qcom,pcie-apq8084\n+\n+ reg:\n+ minItems: 4\n+ maxItems: 5\n+\n+ reg-names:\n+ minItems: 4\n+ items:\n+ - const: parf\n+ - const: dbi\n+ - const: elbi\n+ - const: config\n+ - const: mhi\n+\n+ clocks:\n+ maxItems: 4\n+\n+ clock-names:\n+ items:\n+ - const: iface # Configuration AHB clock\n+ - const: master_bus # Master AXI clock\n+ - const: slave_bus # Slave AXI clock\n+ - const: aux\n+\n+ interrupts:\n+ maxItems: 1\n+\n+ interrupt-names:\n+ items:\n+ - const: msi\n+\n+ resets:\n+ maxItems: 1\n+\n+ reset-names:\n+ items:\n+ - const: core\n+\n+ vdda-supply:\n+ description: A phandle to the core analog power supply\n+\n+required:\n+ - power-domains\n+ - resets\n+ - reset-names\n+\n+allOf:\n+ - $ref: qcom,pcie-common.yaml#\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ #include \n+ #include \n+ pcie@fc520000 {\n+ compatible = \"qcom,pcie-apq8084\";\n+ reg = <0xfc520000 0x2000>,\n+ <0xff000000 0x1000>,\n+ <0xff001000 0x1000>,\n+ <0xff002000 0x2000>;\n+ reg-names = \"parf\", \"dbi\", \"elbi\", \"config\";\n+ device_type = \"pci\";\n+ linux,pci-domain = <0>;\n+ bus-range = <0x00 0xff>;\n+ num-lanes = <1>;\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+ ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,\n+ <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;\n+ interrupts = ;\n+ interrupt-names = \"msi\";\n+ #interrupt-cells = <1>;\n+ interrupt-map-mask = <0 0 0 0x7>;\n+ interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,\n+ <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,\n+ <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,\n+ <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;\n+ clocks = <&gcc 324>,\n+ <&gcc 325>,\n+ <&gcc 327>,\n+ <&gcc 323>;\n+ clock-names = \"iface\", \"master_bus\", \"slave_bus\", \"aux\";\n+ resets = <&gcc 81>;\n+ reset-names = \"core\";\n+ power-domains = <&gcc 1>;\n+ vdda-supply = <&pma8084_l3>;\n+ phys = <&pciephy0>;\n+ phy-names = \"pciephy\";\n+ perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;\n+ pinctrl-0 = <&pcie0_pins_default>;\n+ pinctrl-names = \"default\";\n+ };\ndiff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml\ndeleted file mode 100644\nindex 0d3b49485505..000000000000\n--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml\n+++ /dev/null\n@@ -1,227 +0,0 @@\n-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n-%YAML 1.2\n----\n-$id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#\n-$schema: http://devicetree.org/meta-schemas/core.yaml#\n-\n-title: Qualcomm PCI express root complex\n-\n-maintainers:\n- - Bjorn Andersson \n- - Manivannan Sadhasivam \n-\n-description: |\n- Qualcomm PCIe root complex controller is based on the Synopsys DesignWare\n- PCIe IP.\n-\n-properties:\n- compatible:\n- oneOf:\n- - enum:\n- - qcom,pcie-apq8084\n-\n- reg:\n- minItems: 4\n- maxItems: 6\n-\n- reg-names:\n- minItems: 4\n- maxItems: 6\n-\n- interrupts:\n- minItems: 1\n- maxItems: 9\n-\n- interrupt-names:\n- minItems: 1\n- maxItems: 9\n-\n- iommu-map:\n- minItems: 1\n- maxItems: 16\n-\n- # Common definitions for clocks, clock-names and reset.\n- # Platform constraints are described later.\n- clocks:\n- minItems: 3\n- maxItems: 13\n-\n- clock-names:\n- minItems: 3\n- maxItems: 13\n-\n- dma-coherent: true\n-\n- interconnects:\n- maxItems: 2\n-\n- interconnect-names:\n- items:\n- - const: pcie-mem\n- - const: cpu-pcie\n-\n- resets:\n- minItems: 1\n- maxItems: 12\n-\n- reset-names:\n- minItems: 1\n- maxItems: 12\n-\n- vdda-supply:\n- description: A phandle to the core analog power supply\n-\n- phys:\n- maxItems: 1\n-\n- phy-names:\n- items:\n- - const: pciephy\n-\n- power-domains:\n- maxItems: 1\n-\n- perst-gpios:\n- description: GPIO controlled connection to PERST# signal\n- maxItems: 1\n-\n- required-opps:\n- maxItems: 1\n-\n- wake-gpios:\n- description: GPIO controlled connection to WAKE# signal\n- maxItems: 1\n-\n-required:\n- - compatible\n- - reg\n- - reg-names\n- - interrupt-map-mask\n- - interrupt-map\n- - clocks\n- - clock-names\n-\n-anyOf:\n- - required:\n- - interrupts\n- - interrupt-names\n- - \"#interrupt-cells\"\n- - required:\n- - msi-map\n-\n-allOf:\n- - $ref: /schemas/pci/pci-host-bridge.yaml#\n- - if:\n- properties:\n- compatible:\n- contains:\n- enum:\n- - qcom,pcie-apq8084\n- then:\n- properties:\n- reg:\n- minItems: 4\n- maxItems: 5\n- reg-names:\n- minItems: 4\n- items:\n- - const: parf # Qualcomm specific registers\n- - const: dbi # DesignWare PCIe registers\n- - const: elbi # External local bus interface registers\n- - const: config # PCIe configuration space\n- - const: mhi # MHI registers\n-\n- - if:\n- properties:\n- compatible:\n- contains:\n- enum:\n- - qcom,pcie-apq8084\n- then:\n- properties:\n- clocks:\n- minItems: 4\n- maxItems: 4\n- clock-names:\n- items:\n- - const: iface # Configuration AHB clock\n- - const: master_bus # Master AXI clock\n- - const: slave_bus # Slave AXI clock\n- - const: aux # Auxiliary (AUX) clock\n- resets:\n- maxItems: 1\n- reset-names:\n- items:\n- - const: core # Core reset\n-\n- - if:\n- not:\n- properties:\n- compatible:\n- contains:\n- enum:\n- - qcom,pcie-msm8996\n- then:\n- required:\n- - resets\n- - reset-names\n-\n- - if:\n- properties:\n- compatible:\n- contains:\n- enum:\n- - qcom,pcie-apq8084\n- then:\n- properties:\n- interrupts:\n- maxItems: 1\n- interrupt-names:\n- items:\n- - const: msi\n-\n-unevaluatedProperties: false\n-\n-examples:\n- - |\n- #include \n- #include \n- pcie@fc520000 {\n- compatible = \"qcom,pcie-apq8084\";\n- reg = <0xfc520000 0x2000>,\n- <0xff000000 0x1000>,\n- <0xff001000 0x1000>,\n- <0xff002000 0x2000>;\n- reg-names = \"parf\", \"dbi\", \"elbi\", \"config\";\n- device_type = \"pci\";\n- linux,pci-domain = <0>;\n- bus-range = <0x00 0xff>;\n- num-lanes = <1>;\n- #address-cells = <3>;\n- #size-cells = <2>;\n- ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,\n- <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;\n- interrupts = ;\n- interrupt-names = \"msi\";\n- #interrupt-cells = <1>;\n- interrupt-map-mask = <0 0 0 0x7>;\n- interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,\n- <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,\n- <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,\n- <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;\n- clocks = <&gcc 324>,\n- <&gcc 325>,\n- <&gcc 327>,\n- <&gcc 323>;\n- clock-names = \"iface\", \"master_bus\", \"slave_bus\", \"aux\";\n- resets = <&gcc 81>;\n- reset-names = \"core\";\n- power-domains = <&gcc 1>;\n- vdda-supply = <&pma8084_l3>;\n- phys = <&pciephy0>;\n- phy-names = \"pciephy\";\n- perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;\n- pinctrl-0 = <&pcie0_pins_default>;\n- pinctrl-names = \"default\";\n- };\n-...\n","prefixes":["v2","12/12"]}