{"id":2175239,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175239/?format=json","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.0/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20251217-dt-bindings-pci-qcom-v2-1-873721599754@oss.qualcomm.com>","date":"2025-12-17T16:19:07","name":"[v2,01/12] dt-bindings: PCI: qcom,pcie-sm8150: Merge SC8180x into SM8150","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"491e5ee66befe554c1026906981cae3a19ae52af","submitter":{"id":92171,"url":"http://patchwork.ozlabs.org/api/1.0/people/92171/?format=json","name":"Krzysztof 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<20251217-dt-bindings-pci-qcom-v2-0-873721599754@oss.qualcomm.com>","To":"Bjorn Helgaas ,\n Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= ,\n Manivannan Sadhasivam , Rob Herring ,\n Krzysztof Kozlowski , Conor Dooley ,\n Bjorn Andersson ","Cc":"linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n Krzysztof Kozlowski ","X-Mailer":"b4 0.14.3","X-Developer-Signature":"v=1; a=openpgp-sha256; l=6957;\n i=krzysztof.kozlowski@oss.qualcomm.com; h=from:subject:message-id;\n bh=Fm/yq5Cq8klq4CkYmEM+bbcSx8udY9AgBOJpvYHYnz8=;\n b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBpQtf8kHOUu9hqnWAN4qIze7nN7GMawqQLhbRTV\n jS2xn2IKz6JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaULX/AAKCRDBN2bmhouD\n 14CIEACE6CA5CQ8pgZN591n9ToOp0PZccD1CwSZl6l+hwmFfJR/aP0F/LtCHHjcD5RLABnzb7vF\n XKfmFGJBVOQUNnUYyeGrOOjCUQIN1EtyOfbZIS0k9nyc5jIFrjkuXHwRpH+cY74RqXslCDpKAkI\n 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impostorscore=0\n adultscore=0 priorityscore=1501 phishscore=0 bulkscore=0 malwarescore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512170128"},"content":"After the commit 26daa18e35eb (\"dt-bindings: PCI: qcom,pcie-sc8180x:\nDrop unrelated clocks from PCIe hosts\") and the\ncommit e1cb67ab82aa (\"dt-bindings: PCI: qcom,pcie-sm8150: Drop unrelated\nclocks from PCIe hosts\"), which dropped two clocks from each of the\nbindings, the devices share entire binding and could be kept in one file\nfor simplicity.\n\nReviewed-by: Rob Herring (Arm) \nSigned-off-by: Krzysztof Kozlowski \n---\n .../devicetree/bindings/pci/qcom,pcie-sc8180x.yaml | 168 ---------------------\n .../devicetree/bindings/pci/qcom,pcie-sm8150.yaml | 1 +\n 2 files changed, 1 insertion(+), 168 deletions(-)","diff":"diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml\ndeleted file mode 100644\nindex 6a7c410c9fc3..000000000000\n--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml\n+++ /dev/null\n@@ -1,168 +0,0 @@\n-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n-%YAML 1.2\n----\n-$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml#\n-$schema: http://devicetree.org/meta-schemas/core.yaml#\n-\n-title: Qualcomm SC8180x PCI Express Root Complex\n-\n-maintainers:\n- - Bjorn Andersson \n- - Manivannan Sadhasivam \n-\n-description:\n- Qualcomm SC8180x SoC PCIe root complex controller is based on the Synopsys\n- DesignWare PCIe IP.\n-\n-properties:\n- compatible:\n- const: qcom,pcie-sc8180x\n-\n- reg:\n- minItems: 5\n- maxItems: 6\n-\n- reg-names:\n- minItems: 5\n- items:\n- - const: parf # Qualcomm specific registers\n- - const: dbi # DesignWare PCIe registers\n- - const: elbi # External local bus interface registers\n- - const: atu # ATU address space\n- - const: config # PCIe configuration space\n- - const: mhi # MHI registers\n-\n- clocks:\n- minItems: 6\n- maxItems: 6\n-\n- clock-names:\n- items:\n- - const: pipe # PIPE clock\n- - const: aux # Auxiliary clock\n- - const: cfg # Configuration clock\n- - const: bus_master # Master AXI clock\n- - const: bus_slave # Slave AXI clock\n- - const: slave_q2a # Slave Q2A clock\n-\n- interrupts:\n- minItems: 8\n- maxItems: 9\n-\n- interrupt-names:\n- minItems: 8\n- items:\n- - const: msi0\n- - const: msi1\n- - const: msi2\n- - const: msi3\n- - const: msi4\n- - const: msi5\n- - const: msi6\n- - const: msi7\n- - const: global\n-\n- resets:\n- maxItems: 1\n-\n- reset-names:\n- items:\n- - const: pci\n-\n-allOf:\n- - $ref: qcom,pcie-common.yaml#\n-\n-unevaluatedProperties: false\n-\n-examples:\n- - |\n- #include \n- #include \n- #include \n-\n- soc {\n- #address-cells = <2>;\n- #size-cells = <2>;\n-\n- pcie@1c00000 {\n- compatible = \"qcom,pcie-sc8180x\";\n- reg = <0 0x01c00000 0 0x3000>,\n- <0 0x60000000 0 0xf1d>,\n- <0 0x60000f20 0 0xa8>,\n- <0 0x60001000 0 0x1000>,\n- <0 0x60100000 0 0x100000>;\n- reg-names = \"parf\",\n- \"dbi\",\n- \"elbi\",\n- \"atu\",\n- \"config\";\n- ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,\n- <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;\n-\n- bus-range = <0x00 0xff>;\n- device_type = \"pci\";\n- linux,pci-domain = <0>;\n- num-lanes = <2>;\n-\n- #address-cells = <3>;\n- #size-cells = <2>;\n-\n- assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;\n- assigned-clock-rates = <19200000>;\n-\n- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,\n- <&gcc GCC_PCIE_0_AUX_CLK>,\n- <&gcc GCC_PCIE_0_CFG_AHB_CLK>,\n- <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,\n- <&gcc GCC_PCIE_0_SLV_AXI_CLK>,\n- <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;\n- clock-names = \"pipe\",\n- \"aux\",\n- \"cfg\",\n- \"bus_master\",\n- \"bus_slave\",\n- \"slave_q2a\";\n-\n- dma-coherent;\n-\n- interrupts = ,\n- ,\n- ,\n- ,\n- ,\n- ,\n- ,\n- ,\n- ;\n- interrupt-names = \"msi0\",\n- \"msi1\",\n- \"msi2\",\n- \"msi3\",\n- \"msi4\",\n- \"msi5\",\n- \"msi6\",\n- \"msi7\",\n- \"global\";\n- #interrupt-cells = <1>;\n- interrupt-map-mask = <0 0 0 0x7>;\n- interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */\n- <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */\n- <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */\n- <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */\n-\n- interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,\n- <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;\n- interconnect-names = \"pcie-mem\", \"cpu-pcie\";\n-\n- iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,\n- <0x100 &apps_smmu 0x1d81 0x1>;\n-\n- phys = <&pcie0_phy>;\n- phy-names = \"pciephy\";\n-\n- power-domains = <&gcc PCIE_0_GDSC>;\n-\n- resets = <&gcc GCC_PCIE_0_BCR>;\n- reset-names = \"pci\";\n- };\n- };\ndiff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml\nindex 6a5421e4f19d..ea29d0900a25 100644\n--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml\n+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml\n@@ -17,6 +17,7 @@ description:\n properties:\n compatible:\n oneOf:\n+ - const: qcom,pcie-sc8180x\n - const: qcom,pcie-sm8150\n - items:\n - enum:\n","prefixes":["v2","01/12"]}