{"id":2175223,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175223/?format=json","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.0/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20251217151609.3162665-23-den@valinux.co.jp>","date":"2025-12-17T15:15:56","name":"[RFC,v3,22/35] dmaengine: dw-edma: Serialize RMW on shared interrupt registers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0ced193ab9553e1de73cbc85597bccd325d7cd3a","submitter":{"id":91573,"url":"http://patchwork.ozlabs.org/api/1.0/people/91573/?format=json","name":"Koichiro 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","To":"Frank.Li@nxp.com,\n\tdave.jiang@intel.com,\n\tntb@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tdmaengine@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tnetdev@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Cc":"mani@kernel.org,\n\tkwilczynski@kernel.org,\n\tkishon@kernel.org,\n\tbhelgaas@google.com,\n\tcorbet@lwn.net,\n\tgeert+renesas@glider.be,\n\tmagnus.damm@gmail.com,\n\trobh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tvkoul@kernel.org,\n\tjoro@8bytes.org,\n\twill@kernel.org,\n\trobin.murphy@arm.com,\n\tjdmason@kudzu.us,\n\tallenbh@gmail.com,\n\tandrew+netdev@lunn.ch,\n\tdavem@davemloft.net,\n\tedumazet@google.com,\n\tkuba@kernel.org,\n\tpabeni@redhat.com,\n\tBasavaraj.Natikar@amd.com,\n\tShyam-sundar.S-k@amd.com,\n\tkurt.schwemmer@microsemi.com,\n\tlogang@deltatee.com,\n\tjingoohan1@gmail.com,\n\tlpieralisi@kernel.org,\n\tutkarsh02t@gmail.com,\n\tjbrunet@baylibre.com,\n\tdlemoal@kernel.org,\n\tarnd@arndb.de,\n\telfring@users.sourceforge.net,\n\tden@valinux.co.jp","Subject":"[RFC PATCH v3 22/35] dmaengine: dw-edma: Serialize RMW on shared\n interrupt registers","Date":"Thu, 18 Dec 2025 00:15:56 +0900","Message-ID":"<20251217151609.3162665-23-den@valinux.co.jp>","X-Mailer":"git-send-email 2.51.0","In-Reply-To":"<20251217151609.3162665-1-den@valinux.co.jp>","References":"<20251217151609.3162665-1-den@valinux.co.jp>","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"TYCP286CA0037.JPNP286.PROD.OUTLOOK.COM\n (2603:1096:400:29d::12) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM\n 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34da8626-ba19-4028-b25d-08de3d7f4345","X-MS-Exchange-CrossTenant-AuthSource":"TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"17 Dec 2025 15:16:33.2599\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"7a57bee8-f73d-4c5f-a4f7-d72c91c8c111","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n laA8zGsySCfMmyY/45k+plZwxPHyywrdl9V7G1SkQI/d5XdeVUnzHMcP7EfmT0qGVlbNZov4XbUmwWdM3zUGBg==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"TYCP286MB2863"},"content":"The per-direction int_mask and linked_list_err_en registers are shared\nbetween all channels. Updating them requires a read-modify-write\nsequence, which can lose concurrent updates when multiple channels are\nstarted in parallel. This may leave interrupts masked and stall\ntransfers under high load.\n\nProtect the RMW sequences with dw->lock.\n\nSigned-off-by: Koichiro Den \n---\n drivers/dma/dw-edma/dw-edma-core.h | 3 ++-\n drivers/dma/dw-edma/dw-edma-v0-core.c | 13 ++++++++++---\n 2 files changed, 12 insertions(+), 4 deletions(-)","diff":"diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-edma-core.h\nindex f652d2e38843..d393976a8bfc 100644\n--- a/drivers/dma/dw-edma/dw-edma-core.h\n+++ b/drivers/dma/dw-edma/dw-edma-core.h\n@@ -118,7 +118,8 @@ struct dw_edma {\n \n \tstruct dw_edma_chan\t\t*chan;\n \n-\traw_spinlock_t\t\t\tlock;\t\t/* Only for legacy */\n+\t/* For legacy + shared regs RMW among channels */\n+\traw_spinlock_t\t\t\tlock;\n \n \tstruct dw_edma_chip *chip;\n \ndiff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c\nindex 42a254eb9379..770b011ba3e4 100644\n--- a/drivers/dma/dw-edma/dw-edma-v0-core.c\n+++ b/drivers/dma/dw-edma/dw-edma-v0-core.c\n@@ -369,7 +369,8 @@ static void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)\n {\n \tstruct dw_edma_chan *chan = chunk->chan;\n \tstruct dw_edma *dw = chan->dw;\n-\tu32 tmp;\n+\tunsigned long flags;\n+\tu32 tmp, orig;\n \n \tdw_edma_v0_core_write_chunk(chunk);\n \n@@ -413,7 +414,9 @@ static void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)\n \t\t\t}\n \t\t}\n \t\t/* Interrupt mask/unmask - done, abort */\n+\t\traw_spin_lock_irqsave(&dw->lock, flags);\n \t\ttmp = GET_RW_32(dw, chan->dir, int_mask);\n+\t\torig = tmp;\n \t\tif (chan->irq_mode == DW_EDMA_CH_IRQ_REMOTE) {\n \t\t\ttmp |= FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id));\n \t\t\ttmp |= FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id));\n@@ -421,11 +424,15 @@ static void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)\n \t\t\ttmp &= ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id));\n \t\t\ttmp &= ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id));\n \t\t}\n-\t\tSET_RW_32(dw, chan->dir, int_mask, tmp);\n+\t\tif (tmp != orig)\n+\t\t\tSET_RW_32(dw, chan->dir, int_mask, tmp);\n \t\t/* Linked list error */\n \t\ttmp = GET_RW_32(dw, chan->dir, linked_list_err_en);\n+\t\torig = tmp;\n \t\ttmp |= FIELD_PREP(EDMA_V0_LINKED_LIST_ERR_MASK, BIT(chan->id));\n-\t\tSET_RW_32(dw, chan->dir, linked_list_err_en, tmp);\n+\t\tif (tmp != orig)\n+\t\t\tSET_RW_32(dw, chan->dir, linked_list_err_en, tmp);\n+\t\traw_spin_unlock_irqrestore(&dw->lock, flags);\n \t\t/* Channel control */\n \t\tSET_CH_32(dw, chan->dir, chan->id, ch_control1,\n \t\t\t (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE));\n","prefixes":["RFC","v3","22/35"]}