{"id":2175206,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175206/?format=json","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.0/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20251217151609.3162665-30-den@valinux.co.jp>","date":"2025-12-17T15:16:03","name":"[RFC,v3,29/35] NTB: epf: Add per-SoC quirk to cap MRRS for DWC eDMA (128B for R-Car)","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"85d0d3a80068445ee5bde9c633fd3bf6d765aa6e","submitter":{"id":91573,"url":"http://patchwork.ozlabs.org/api/1.0/people/91573/?format=json","name":"Koichiro Den","email":"den@valinux.co.jp"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20251217151609.3162665-30-den@valinux.co.jp/mbox/","series":[{"id":485709,"url":"http://patchwork.ozlabs.org/api/1.0/series/485709/?format=json","date":"2025-12-17T15:15:53","name":"NTB transport backed by endpoint DW eDMA","version":3,"mbox":"http://patchwork.ozlabs.org/series/485709/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175206/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=valinux.co.jp header.i=@valinux.co.jp\n header.a=rsa-sha256 header.s=selector1 header.b=rPuhCfeq;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n 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bh=fGCTgygFHcBT4UMiTZRF4kncO36Fu1a7I/tGPUBEN0I=;\n b=rPuhCfeq3Jn8Uo56hRV9IH8kVmavYoOZ28FZNx/H+ll51odi59hFY1V9F8twTDB/O4Vjt4PdfoR+N0q57SSKdUQQ8jhFf9C0ysTX8qR25zhn2AW4a8nyLcliRdpd8T9u+cvXDm3kPGmivQq9wJTP7YBkbzzl13KVuETdlaK9sPA=","From":"Koichiro Den ","To":"Frank.Li@nxp.com,\n\tdave.jiang@intel.com,\n\tntb@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tdmaengine@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tnetdev@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Cc":"mani@kernel.org,\n\tkwilczynski@kernel.org,\n\tkishon@kernel.org,\n\tbhelgaas@google.com,\n\tcorbet@lwn.net,\n\tgeert+renesas@glider.be,\n\tmagnus.damm@gmail.com,\n\trobh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tvkoul@kernel.org,\n\tjoro@8bytes.org,\n\twill@kernel.org,\n\trobin.murphy@arm.com,\n\tjdmason@kudzu.us,\n\tallenbh@gmail.com,\n\tandrew+netdev@lunn.ch,\n\tdavem@davemloft.net,\n\tedumazet@google.com,\n\tkuba@kernel.org,\n\tpabeni@redhat.com,\n\tBasavaraj.Natikar@amd.com,\n\tShyam-sundar.S-k@amd.com,\n\tkurt.schwemmer@microsemi.com,\n\tlogang@deltatee.com,\n\tjingoohan1@gmail.com,\n\tlpieralisi@kernel.org,\n\tutkarsh02t@gmail.com,\n\tjbrunet@baylibre.com,\n\tdlemoal@kernel.org,\n\tarnd@arndb.de,\n\telfring@users.sourceforge.net,\n\tden@valinux.co.jp","Subject":"[RFC PATCH v3 29/35] NTB: epf: Add per-SoC quirk to cap MRRS for DWC\n eDMA (128B for R-Car)","Date":"Thu, 18 Dec 2025 00:16:03 +0900","Message-ID":"<20251217151609.3162665-30-den@valinux.co.jp>","X-Mailer":"git-send-email 2.51.0","In-Reply-To":"<20251217151609.3162665-1-den@valinux.co.jp>","References":"<20251217151609.3162665-1-den@valinux.co.jp>","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"TY4P301CA0005.JPNP301.PROD.OUTLOOK.COM\n (2603:1096:405:26f::9) To TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM\n 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qiRxN8GdRJwFGPVsFTPfMTuMrQy7M8+ND54WQ1n842IyjXCRIwO0uwzQ37g8ncfVlnwzq15BtLTgS44NBs6JQsmtoWqCBwsd3vjPRt82oiqbQsjvbhLm7GPXO5kmjLdt1svijAShTftK6UT/XznKWnvOnWt3TTwintC0XxnuxfzfUF3Jw5jOuH6Kn1dZquWBbg2Gt/1yhFA+kyQGxSpAn35vmtGcaBnBlV5ofHw2Yl6RQ2v9v+t9HM9d9fst5lHLL5wcDJReUsWNEotyNzKLLq/MxhnkZGtDKbyqdALPt+kcwQHcwvpDDKEW+HW3R02qeJ5N+SB6qiCwRKs5lai22sk04PxG9XogIM98kbRBD1El1n1QEIN5I/QalLF0e29MsLeaDo3rbbYDgxGKtM4631yI+g8r6OQE1t5wAcsOP0NA2BgXCqEq+6NhEr9Y+/3wCNyFX1k530gdv7bxS7CDqNmKEuHakDGJ2gIGoV8vu4jy2jQgevBUHha2Ht+JrbSlw1dChiZK2aJJh/atlGf80Won6gSqfSZDVcQKb0zRnEN6IjiangjJHkz1e1HH1PyaO4Yw8jA6Mp4E5pCGfey+qg5iS4bPkOQ+YfZdRlwdM6+9XOPwvxt4zX6nU9POK2aXrcMNq6JIqUgg9uXKc2NkqH7WVKHHzENUNc9/FOTaCi9uQv9BgYYoWHpPW9bOzx5Y0QAZDwt8gKoFKgb1AUvT7eibqJp3WJrzEHFgsZATsqvU7AkazMbieQqVihxBPjhcMyxw5VbYkshN6h5xXO5WgHdqhx1u9MyzFM1tulmBeNSxMHk/FNrzPemh1PhkUZGnhxjjAQ20wpdwkrRuX08Sp3kKvrO1HpMYNvtnTu0xk76SEUpt0OYT5efhJwQOEobTk3Nrpn5KFpTIiTmj6jWz5+6RXbmnkGgUjNCLdzfODX6YqHBw71QehvWl1aIbl/xZsgi7Jx99sddOY9N7qNWuPKe7BNA8PBOQ7fulO89KapxMc1L8a/YbYO0w9hVV41sOhNLncJM43buZSeuobo/33iYFJvRW30M2c32F4/5KbJ9loJWzGsuQPBHGVnXa9d1mcenlX+1FwzdkUBDem3On3zFRlC6kD4rgoS3bMv2dXHeknfD9znW7Zp+MBhg5JyVtZeAtb2+pF6HKsfUYdruO1iN8qlla48R5OFZeRfKpUx35ucSGA5bz17hSqsNB7YjJI8jc9o1nD7VU3PvzEXrYC0CnPpWWWMKVxb3fysLbrPh0MWNa7ncIm3Xoopx1JdWRmYkXk/u8UloUWnBe+DDxJN+ijE1PGGmVilqWMbDstknrmnDIY4TKCTrCcT33AAAWIkqCjzP5dA74lym7IXSE2HgkVv6iNbC93NDDtUYlw5l1cI9SoFaTo1FXFuv1KbSTf6s2XGJuKe/5V3ed4sIF4BOyb3OjFk8REoB6oLVD+F4NlreRKDbhInOkqtxI5ez0dh3Zp8+3FMOR5dIysD/pJFTp+umcxt/KLcfDWYOpncjh5SyUL2+JMc9GcOB0s0pnYKg2T4lgye9a/5u6Na9Z/x7vXaCu3iFptKLSSOwlDOy2btX7+Z6mnwWXoLAR8BZQ7sxf0mSQ5gDIwqmOiN9jiWXkI3mnG0ni2a3F5ZQE4Ic=","X-OriginatorOrg":"valinux.co.jp","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 0a7de7a2-4218-4c83-0d26-08de3d7f4757","X-MS-Exchange-CrossTenant-AuthSource":"TYWP286MB2697.JPNP286.PROD.OUTLOOK.COM","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"17 Dec 2025 15:16:40.0862\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"7a57bee8-f73d-4c5f-a4f7-d72c91c8c111","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n F9kQBDRlVH61IbI2v1DnVQAF6q9WKPe2/Sf5dF+pU8zt0yE3t4SAIxHWL8fK38K0J5J/EPx4ZWKkhuu239XybA==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"TYCP286MB2863"},"content":"Some R-Car platforms using Synopsys DesignWare PCIe with the integrated\neDMA exhibit reproducible payload corruption in RC->EP remote DMA read\ntraffic whenever the endpoint issues 256-byte Memory Read (MRd) TLPs.\n\nThe eDMA injects multiple MRd requests of size less than or equal to\nmin(MRRS, MPS), so constraining the endpoint's MRd request size removes\n256-byte MRd TLPs and avoids the issue. This change adds a per-SoC knob\nin the ntb_hw_epf driver and sets MRRS=128 on R-Car.\n\nWe intentionally do not change the endpoint's MPS. Per PCIe Base\nSpecification, MPS limits the payload size of TLPs with data transmitted\nby the Function, while Max_Read_Request_Size limits the size of read\nrequests produced by the Function as a Requester. Limiting MRRS is\nsufficient to constrain MRd Byte Count, while lowering MPS would also\nthrottle unrelated traffic (e.g. endpoint-originated Posted Writes and\nCompletions with Data) without being necessary for this fix.\n\nThis quirk is scoped to the affected endpoint only and can be removed\nonce the underlying issue is resolved in the controller/IP.\n\nReviewed-by: Frank Li \nSigned-off-by: Koichiro Den \n---\n drivers/ntb/hw/epf/ntb_hw_epf.c | 66 +++++++++++++++++++++++++++++----\n 1 file changed, 58 insertions(+), 8 deletions(-)","diff":"diff --git a/drivers/ntb/hw/epf/ntb_hw_epf.c b/drivers/ntb/hw/epf/ntb_hw_epf.c\nindex 5303a8944019..efe540a8c734 100644\n--- a/drivers/ntb/hw/epf/ntb_hw_epf.c\n+++ b/drivers/ntb/hw/epf/ntb_hw_epf.c\n@@ -74,6 +74,12 @@ enum epf_ntb_bar {\n \tNTB_BAR_NUM,\n };\n \n+struct ntb_epf_soc_data {\n+\tconst enum pci_barno *barno_map;\n+\t/* non-zero to override MRRS for this SoC */\n+\tint force_mrrs;\n+};\n+\n #define NTB_EPF_MAX_MW_COUNT\t(NTB_BAR_NUM - BAR_MW1)\n \n struct ntb_epf_dev {\n@@ -624,11 +630,12 @@ static int ntb_epf_init_dev(struct ntb_epf_dev *ndev)\n }\n \n static int ntb_epf_init_pci(struct ntb_epf_dev *ndev,\n-\t\t\t struct pci_dev *pdev)\n+\t\t\t struct pci_dev *pdev,\n+\t\t\t const struct ntb_epf_soc_data *soc)\n {\n \tstruct device *dev = ndev->dev;\n \tsize_t spad_sz, spad_off;\n-\tint ret;\n+\tint ret, cur;\n \n \tpci_set_drvdata(pdev, ndev);\n \n@@ -646,6 +653,17 @@ static int ntb_epf_init_pci(struct ntb_epf_dev *ndev,\n \n \tpci_set_master(pdev);\n \n+\tif (soc && pci_is_pcie(pdev) && soc->force_mrrs) {\n+\t\tcur = pcie_get_readrq(pdev);\n+\t\tret = pcie_set_readrq(pdev, soc->force_mrrs);\n+\t\tif (ret)\n+\t\t\tdev_warn(&pdev->dev, \"failed to set MRRS=%d: %d\\n\",\n+\t\t\t\t soc->force_mrrs, ret);\n+\t\telse\n+\t\t\tdev_info(&pdev->dev, \"capped MRRS: %d->%d for ntb-epf\\n\",\n+\t\t\t\t cur, soc->force_mrrs);\n+\t}\n+\n \tret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));\n \tif (ret) {\n \t\tret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));\n@@ -720,6 +738,7 @@ static void ntb_epf_cleanup_isr(struct ntb_epf_dev *ndev)\n static int ntb_epf_pci_probe(struct pci_dev *pdev,\n \t\t\t const struct pci_device_id *id)\n {\n+\tconst struct ntb_epf_soc_data *soc = (const void *)id->driver_data;\n \tstruct device *dev = &pdev->dev;\n \tstruct ntb_epf_dev *ndev;\n \tint ret;\n@@ -731,16 +750,16 @@ static int ntb_epf_pci_probe(struct pci_dev *pdev,\n \tif (!ndev)\n \t\treturn -ENOMEM;\n \n-\tndev->barno_map = (const enum pci_barno *)id->driver_data;\n-\tif (!ndev->barno_map)\n+\tif (!soc || !soc->barno_map)\n \t\treturn -EINVAL;\n \n+\tndev->barno_map = soc->barno_map;\n \tndev->dev = dev;\n \n \tntb_epf_init_struct(ndev, pdev);\n \tmutex_init(&ndev->cmd_lock);\n \n-\tret = ntb_epf_init_pci(ndev, pdev);\n+\tret = ntb_epf_init_pci(ndev, pdev, soc);\n \tif (ret) {\n \t\tdev_err(dev, \"Failed to init PCI\\n\");\n \t\treturn ret;\n@@ -812,21 +831,52 @@ static const enum pci_barno rcar_barno[NTB_BAR_NUM] = {\n \t[BAR_MW4]\t= NO_BAR,\n };\n \n+static const struct ntb_epf_soc_data j721e_soc = {\n+\t.barno_map = j721e_map,\n+};\n+\n+static const struct ntb_epf_soc_data mx8_soc = {\n+\t.barno_map = mx8_map,\n+};\n+\n+static const struct ntb_epf_soc_data rcar_soc = {\n+\t.barno_map = rcar_barno,\n+\t/*\n+\t * On some R-Car platforms using the Synopsys DWC PCIe + eDMA we\n+\t * observe data corruption on RC->EP Remote DMA Read paths whenever\n+\t * the EP issues large MRd requests. The corruption consistently\n+\t * hits the tail of each 256-byte segment (e.g. offsets\n+\t * 0x00E0..0x00FF within a 256B block, and again at 0x01E0..0x01FF\n+\t * for larger transfers).\n+\t *\n+\t * The DMA injects multiple MRd requests of size less than or equal\n+\t * to the min(MRRS, MPS) into the outbound request path. By\n+\t * lowering MRRS to 128 we prevent 256B MRd TLPs from being\n+\t * generated and avoid the issue on the affected hardware. We\n+\t * intentionally keep MPS unchanged and scope this quirk to this\n+\t * endpoint to avoid impacting unrelated devices.\n+\t *\n+\t * Remove this once the issue is resolved (maybe controller/IP\n+\t * level) or a more preferable workaround becomes available.\n+\t */\n+\t.force_mrrs = 128,\n+};\n+\n static const struct pci_device_id ntb_epf_pci_tbl[] = {\n \t{\n \t\tPCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),\n \t\t.class = PCI_CLASS_MEMORY_RAM << 8, .class_mask = 0xffff00,\n-\t\t.driver_data = (kernel_ulong_t)j721e_map,\n+\t\t.driver_data = (kernel_ulong_t)&j721e_soc,\n \t},\n \t{\n \t\tPCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x0809),\n \t\t.class = PCI_CLASS_MEMORY_RAM << 8, .class_mask = 0xffff00,\n-\t\t.driver_data = (kernel_ulong_t)mx8_map,\n+\t\t.driver_data = (kernel_ulong_t)&mx8_soc,\n \t},\n \t{\n \t\tPCI_DEVICE(PCI_VENDOR_ID_RENESAS, 0x0030),\n \t\t.class = PCI_CLASS_MEMORY_RAM << 8, .class_mask = 0xffff00,\n-\t\t.driver_data = (kernel_ulong_t)rcar_barno,\n+\t\t.driver_data = (kernel_ulong_t)&rcar_soc,\n \t},\n \t{ },\n };\n","prefixes":["RFC","v3","29/35"]}