{"id":2175185,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175185/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20251217143150.94463-14-philmd@linaro.org>","date":"2025-12-17T14:31:49","name":"[13/14] system/memory: Pass device_endian argument as MemOp bit","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"fd66a8d24adafe9dd014356242eb3b90b1ea31ea","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/1.0/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20251217143150.94463-14-philmd@linaro.org/mbox/","series":[{"id":485701,"url":"http://patchwork.ozlabs.org/api/1.0/series/485701/?format=json","date":"2025-12-17T14:31:37","name":"system/memory: Clean ups around address_space_ldst() endian variants","version":1,"mbox":"http://patchwork.ozlabs.org/series/485701/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175185/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=GH2MbCMP;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Tsirkin\" ,\n Artyom Tarasenko ,\n Peter Maydell ,\n David Hildenbrand , Peter Xu ","Subject":"[PATCH 13/14] system/memory: Pass device_endian argument as MemOp bit","Date":"Wed, 17 Dec 2025 15:31:49 +0100","Message-ID":"<20251217143150.94463-14-philmd@linaro.org>","X-Mailer":"git-send-email 2.52.0","In-Reply-To":"<20251217143150.94463-1-philmd@linaro.org>","References":"<20251217143150.94463-1-philmd@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::344;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x344.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Use the MemOp argument to hold both the access size and\nits endianness.\n\nSigned-off-by: Philippe Mathieu-Daudé \n---\n system/memory_ldst.c.inc | 86 ++++++++++++---------------------\n system/memory_ldst_endian.c.inc | 20 +++-----\n 2 files changed, 38 insertions(+), 68 deletions(-)","diff":"diff --git a/system/memory_ldst.c.inc b/system/memory_ldst.c.inc\nindex e0c0c3f5dca..6387bb9d332 100644\n--- a/system/memory_ldst.c.inc\n+++ b/system/memory_ldst.c.inc\n@@ -24,8 +24,7 @@ static inline\n uint64_t glue(address_space_ldm_internal, SUFFIX)(ARG1_DECL, MemOp mop,\n hwaddr addr,\n MemTxAttrs attrs,\n- MemTxResult *result,\n- enum device_endian endian)\n+ MemTxResult *result)\n {\n const unsigned size = memop_size(mop);\n uint8_t *ptr;\n@@ -42,22 +41,15 @@ uint64_t glue(address_space_ldm_internal, SUFFIX)(ARG1_DECL, MemOp mop,\n release_lock |= prepare_mmio_access(mr);\n \n /* I/O case */\n- r = memory_region_dispatch_read(mr, addr1, &val,\n- mop | devend_memop(endian), attrs);\n+ r = memory_region_dispatch_read(mr, addr1, &val, mop, attrs);\n } else {\n /* RAM case */\n fuzz_dma_read_cb(addr, size, mr);\n ptr = qemu_map_ram_ptr(mr->ram_block, addr1);\n- switch (endian) {\n- case DEVICE_LITTLE_ENDIAN:\n+ if ((mop & MO_BSWAP) == MO_LE) {\n val = ldn_le_p(ptr, size);\n- break;\n- case DEVICE_BIG_ENDIAN:\n+ } else {\n val = ldn_be_p(ptr, size);\n- break;\n- default:\n- val = ldn_p(ptr, size);\n- break;\n }\n r = MEMTX_OK;\n }\n@@ -73,45 +65,40 @@ uint64_t glue(address_space_ldm_internal, SUFFIX)(ARG1_DECL, MemOp mop,\n \n /* warning: addr must be aligned */\n static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,\n- hwaddr addr, MemTxAttrs attrs, MemTxResult *result,\n- enum device_endian endian)\n+ MemOp mop, hwaddr addr, MemTxAttrs attrs, MemTxResult *result)\n {\n- return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_32, addr,\n- attrs, result, endian);\n+ return glue(address_space_ldm_internal, SUFFIX)(ARG1, mop | MO_32, addr,\n+ attrs, result);\n }\n \n /* warning: addr must be aligned */\n static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,\n- hwaddr addr, MemTxAttrs attrs, MemTxResult *result,\n- enum device_endian endian)\n+ MemOp mop, hwaddr addr, MemTxAttrs attrs, MemTxResult *result)\n {\n- return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_64, addr,\n- attrs, result, endian);\n+ return glue(address_space_ldm_internal, SUFFIX)(ARG1, mop | MO_64, addr,\n+ attrs, result);\n }\n \n uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,\n hwaddr addr, MemTxAttrs attrs, MemTxResult *result)\n {\n return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_8, addr,\n- attrs, result,\n- DEVICE_NATIVE_ENDIAN);\n+ attrs, result);\n }\n \n /* warning: addr must be aligned */\n static inline uint16_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,\n- hwaddr addr, MemTxAttrs attrs, MemTxResult *result,\n- enum device_endian endian)\n+ MemOp mop, hwaddr addr, MemTxAttrs attrs, MemTxResult *result)\n {\n- return glue(address_space_ldm_internal, SUFFIX)(ARG1, MO_16, addr,\n- attrs, result, endian);\n+ return glue(address_space_ldm_internal, SUFFIX)(ARG1, mop | MO_16, addr,\n+ attrs, result);\n }\n \n static inline\n void glue(address_space_stm_internal, SUFFIX)(ARG1_DECL, MemOp mop,\n hwaddr addr, uint64_t val,\n MemTxAttrs attrs,\n- MemTxResult *result,\n- enum device_endian endian)\n+ MemTxResult *result)\n {\n const unsigned size = memop_size(mop);\n uint8_t *ptr;\n@@ -125,21 +112,14 @@ void glue(address_space_stm_internal, SUFFIX)(ARG1_DECL, MemOp mop,\n mr = TRANSLATE(addr, &addr1, &l, true, attrs);\n if (l < size || !memory_access_is_direct(mr, true, attrs)) {\n release_lock |= prepare_mmio_access(mr);\n- r = memory_region_dispatch_write(mr, addr1, val,\n- mop | devend_memop(endian), attrs);\n+ r = memory_region_dispatch_write(mr, addr1, val, mop, attrs);\n } else {\n /* RAM case */\n ptr = qemu_map_ram_ptr(mr->ram_block, addr1);\n- switch (endian) {\n- case DEVICE_LITTLE_ENDIAN:\n+ if ((mop & MO_BSWAP) == MO_LE) {\n stn_le_p(ptr, size, val);\n- break;\n- case DEVICE_BIG_ENDIAN:\n+ } else {\n stn_be_p(ptr, size, val);\n- break;\n- default:\n- stn_p(ptr, size, val);\n- break;\n }\n invalidate_and_set_dirty(mr, addr1, size);\n r = MEMTX_OK;\n@@ -155,48 +135,44 @@ void glue(address_space_stm_internal, SUFFIX)(ARG1_DECL, MemOp mop,\n \n /* warning: addr must be aligned */\n static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,\n- hwaddr addr, uint32_t val, MemTxAttrs attrs,\n- MemTxResult *result, enum device_endian endian)\n+ MemOp mop, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)\n {\n- glue(address_space_stm_internal, SUFFIX)(ARG1, MO_32, addr, val,\n- attrs, result, endian);\n+ glue(address_space_stm_internal, SUFFIX)(ARG1, mop | MO_32, addr, val,\n+ attrs, result);\n }\n \n void glue(address_space_stb, SUFFIX)(ARG1_DECL,\n hwaddr addr, uint8_t val, MemTxAttrs attrs, MemTxResult *result)\n {\n glue(address_space_stm_internal, SUFFIX)(ARG1, MO_8, addr, val,\n- attrs, result,\n- DEVICE_NATIVE_ENDIAN);\n+ attrs, result);\n }\n \n /* warning: addr must be aligned */\n static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,\n- hwaddr addr, uint16_t val, MemTxAttrs attrs,\n- MemTxResult *result, enum device_endian endian)\n+ MemOp mop, hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result)\n {\n- glue(address_space_stm_internal, SUFFIX)(ARG1, MO_16, addr, val,\n- attrs, result, endian);\n+ glue(address_space_stm_internal, SUFFIX)(ARG1, mop | MO_16, addr, val,\n+ attrs, result);\n }\n \n static inline void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,\n- hwaddr addr, uint64_t val, MemTxAttrs attrs,\n- MemTxResult *result, enum device_endian endian)\n+ MemOp mop, hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)\n {\n- glue(address_space_stm_internal, SUFFIX)(ARG1, MO_64, addr, val,\n- attrs, result, endian);\n+ glue(address_space_stm_internal, SUFFIX)(ARG1, mop | MO_64, addr, val,\n+ attrs, result);\n }\n \n #define ENDIANNESS\n-#define DEVICE_ENDIANNESS DEVICE_NATIVE_ENDIAN\n+#define MO_ENDIAN (target_big_endian() ? MO_BE : MO_LE)\n #include \"memory_ldst_endian.c.inc\"\n \n #define ENDIANNESS _le\n-#define DEVICE_ENDIANNESS DEVICE_LITTLE_ENDIAN\n+#define MO_ENDIAN MO_LE\n #include \"memory_ldst_endian.c.inc\"\n \n #define ENDIANNESS _be\n-#define DEVICE_ENDIANNESS DEVICE_BIG_ENDIAN\n+#define MO_ENDIAN MO_BE\n #include \"memory_ldst_endian.c.inc\"\n \n #undef ARG1_DECL\ndiff --git a/system/memory_ldst_endian.c.inc b/system/memory_ldst_endian.c.inc\nindex 16d686b50f7..8a4b4a3d220 100644\n--- a/system/memory_ldst_endian.c.inc\n+++ b/system/memory_ldst_endian.c.inc\n@@ -22,43 +22,37 @@\n uint16_t ADDRESS_SPACE_LD(uw)(ARG1_DECL, hwaddr addr,\n MemTxAttrs attrs, MemTxResult *result)\n {\n- return ADDRESS_SPACE_LD_INTERNAL(uw)(ARG1, addr, attrs, result,\n- DEVICE_ENDIANNESS);\n+ return ADDRESS_SPACE_LD_INTERNAL(uw)(ARG1, MO_ENDIAN, addr, attrs, result);\n }\n \n uint32_t ADDRESS_SPACE_LD(l)(ARG1_DECL, hwaddr addr,\n MemTxAttrs attrs, MemTxResult *result)\n {\n- return ADDRESS_SPACE_LD_INTERNAL(l)(ARG1, addr, attrs, result,\n- DEVICE_ENDIANNESS);\n+ return ADDRESS_SPACE_LD_INTERNAL(l)(ARG1, MO_ENDIAN, addr, attrs, result);\n }\n \n uint64_t ADDRESS_SPACE_LD(q)(ARG1_DECL, hwaddr addr,\n MemTxAttrs attrs, MemTxResult *result)\n {\n- return ADDRESS_SPACE_LD_INTERNAL(q)(ARG1, addr, attrs, result,\n- DEVICE_ENDIANNESS);\n+ return ADDRESS_SPACE_LD_INTERNAL(q)(ARG1, MO_ENDIAN, addr, attrs, result);\n }\n \n void ADDRESS_SPACE_ST(w)(ARG1_DECL, hwaddr addr, uint16_t val,\n MemTxAttrs attrs, MemTxResult *result)\n {\n- ADDRESS_SPACE_ST_INTERNAL(w)(ARG1, addr, val, attrs, result,\n- DEVICE_ENDIANNESS);\n+ ADDRESS_SPACE_ST_INTERNAL(w)(ARG1, MO_ENDIAN, addr, val, attrs, result);\n }\n \n void ADDRESS_SPACE_ST(l)(ARG1_DECL, hwaddr addr, uint32_t val,\n MemTxAttrs attrs, MemTxResult *result)\n {\n- ADDRESS_SPACE_ST_INTERNAL(l)(ARG1, addr, val, attrs, result,\n- DEVICE_ENDIANNESS);\n+ ADDRESS_SPACE_ST_INTERNAL(l)(ARG1, MO_ENDIAN, addr, val, attrs, result);\n }\n \n void ADDRESS_SPACE_ST(q)(ARG1_DECL, hwaddr addr, uint64_t val,\n MemTxAttrs attrs, MemTxResult *result)\n {\n- ADDRESS_SPACE_ST_INTERNAL(q)(ARG1, addr, val, attrs, result,\n- DEVICE_ENDIANNESS);\n+ ADDRESS_SPACE_ST_INTERNAL(q)(ARG1, MO_ENDIAN, addr, val, attrs, result);\n }\n \n #undef ADDRESS_SPACE_LD\n@@ -67,4 +61,4 @@ void ADDRESS_SPACE_ST(q)(ARG1_DECL, hwaddr addr, uint64_t val,\n #undef ADDRESS_SPACE_ST_INTERNAL\n \n #undef ENDIANNESS\n-#undef DEVICE_ENDIANNESS\n+#undef MO_ENDIAN\n","prefixes":["13/14"]}