{"id":2175114,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175114/?format=json","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.0/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20251217-staging-ad4062-v4-9-7890a2951a8f@analog.com>","date":"2025-12-17T12:13:32","name":"[v4,9/9] iio: adc: ad4062: Add GPIO Controller support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2ea21e11ca6d8e5fb1e8631ea26d9c841c087fd5","submitter":{"id":90425,"url":"http://patchwork.ozlabs.org/api/1.0/people/90425/?format=json","name":"Jorge Marques","email":"jorge.marques@analog.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20251217-staging-ad4062-v4-9-7890a2951a8f@analog.com/mbox/","series":[{"id":485673,"url":"http://patchwork.ozlabs.org/api/1.0/series/485673/?format=json","date":"2025-12-17T12:13:23","name":"Add support for AD4062 device family","version":4,"mbox":"http://patchwork.ozlabs.org/series/485673/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2175114/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=analog.com header.i=@analog.com header.a=rsa-sha256\n header.s=DKIM header.b=sgeD5y49;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-ID":"<20251217-staging-ad4062-v4-9-7890a2951a8f@analog.com>","References":"<20251217-staging-ad4062-v4-0-7890a2951a8f@analog.com>","In-Reply-To":"<20251217-staging-ad4062-v4-0-7890a2951a8f@analog.com>","To":"Lars-Peter Clausen ,\n Michael Hennerich ,\n Jonathan Cameron , David Lechner ,\n\t=?utf-8?q?Nuno_S=C3=A1?= ,\n Andy Shevchenko , Rob Herring ,\n Krzysztof Kozlowski , Conor Dooley ,\n Jonathan Corbet , Linus Walleij ,\n Bartosz Golaszewski ","CC":", ,\n , ,\n ,\n Jorge Marques ,\n Linus\n Walleij ","X-Mailer":"b4 0.14.3","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1765973610; l=5630;\n i=jorge.marques@analog.com; s=20250303; h=from:subject:message-id;\n bh=rWhz1qhXX5cZm+GWRaQ9ciBLBk8IoCqoYZlI/GtAfiU=;\n b=h16QtNehE13q2APVGRNCeEMKpMfldJrbGJvTDRVuABLEbYt7oxYkLRAKNQmg8+ALzaizen8Ym\n oTUbxYvehAQAfOzzKGbEuTXlBrnsFx/opjcwaZoxHAsuIZrsrWNLFup","X-Developer-Key":"i=jorge.marques@analog.com; a=ed25519;\n pk=NUR1IZZMH0Da3QbJ2tBSznSPVfRpuoWdhBzKGSpAdbg=","X-ADIRuleOP-NewSCL":"Rule Triggered","X-Proofpoint-ORIG-GUID":"ckUSgF4LPP59bHdYNifnVx-5YPN-zhUu","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjUxMjE3MDA5NSBTYWx0ZWRfX6dHUfdknNgPL\n 9FVSstJkgNDxfckZxjcWQB2/JmskCToaAi252B97jS86QmiMPPZOOZUUO7pLeJnELJTFScuMOBQ\n gt5ZGmYRyIUsq/hlrSzIXyWwCko4hl9gxChnxYKNeCm2EC/t5P6ApxQbtkMP9ZF1wzdrR7Vz9Rg\n OmSiLmbGzLujoio7rGtGkzsqQ7AZKD9Ts5RlRDcjgeGHFSo1bTjMMdQ/YVIQsZWjmoLJbnDmemq\n iDcNQgvbw/IlYgB9Xj9xzhVqOKee2zw9fbptimU5YqNWcbQ+ZGmAMDV/Fsgzv3ktlpmhhkjMyO7\n 0y6T4xArldYx3tBAetS4ADcVeZ/4/mp3i1/S9kd0I2+HEBoWE68w6C6PJ2mSeSm4VS2nee2dY5q\n ASsFPXI1zFvjycYpCs5DSh0VzMHs2A==","X-Authority-Analysis":"v=2.4 cv=YqsChoYX c=1 sm=1 tr=0 ts=69429e8f cx=c_pps\n a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17\n a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22\n a=gAnH3GRIAAAA:8 a=VwQbUJbxAAAA:8 a=xMyuZJbwAj7bCYiyej4A:9 a=QEXdDO2ut3YA:10","X-Proofpoint-GUID":"ckUSgF4LPP59bHdYNifnVx-5YPN-zhUu","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49\n definitions=2025-12-17_01,2025-12-16_05,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n spamscore=0 malwarescore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0\n phishscore=0 impostorscore=0 clxscore=1011 adultscore=0 priorityscore=1501\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512170095"},"content":"When gp0 or gp1 is not taken as an interrupt, expose them as GPO if\ngpio-contoller is set in the devicetree. gpio-regmap is not used\nbecause the GPO static low is 'b101 and static high is 0b110; low state\nrequires setting bit 0, not fitting the abstraction of low=0 and\nhigh=mask.\n\nSigned-off-by: Jorge Marques \nReviewed-by: Linus Walleij \n---\n drivers/iio/adc/ad4062.c | 125 +++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 125 insertions(+)","diff":"diff --git a/drivers/iio/adc/ad4062.c b/drivers/iio/adc/ad4062.c\nindex 2084f0058627d..a6b3ccc98acfc 100644\n--- a/drivers/iio/adc/ad4062.c\n+++ b/drivers/iio/adc/ad4062.c\n@@ -11,6 +11,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n #include \n@@ -88,8 +89,11 @@\n #define AD4060_PROD_ID\t\t0x7A\n #define AD4062_PROD_ID\t\t0x7C\n \n+#define AD4062_GP_DISABLED\t0x0\n #define AD4062_GP_INTR\t\t0x1\n #define AD4062_GP_DRDY\t\t0x2\n+#define AD4062_GP_STATIC_LOW\t0x5\n+#define AD4062_GP_STATIC_HIGH\t0x6\n \n #define AD4062_LIMIT_BITS\t12\n \n@@ -687,12 +691,14 @@ static int ad4062_request_irq(struct iio_dev *indio_dev)\n \t\treturn ret;\n \n \tif (ret < 0) {\n+\t\tst->gpo_irq[0] = false;\n \t\tret = regmap_update_bits(st->regmap, AD4062_REG_ADC_IBI_EN,\n \t\t\t\t\t AD4062_REG_ADC_IBI_EN_MAX | AD4062_REG_ADC_IBI_EN_MIN,\n \t\t\t\t\t AD4062_REG_ADC_IBI_EN_MAX | AD4062_REG_ADC_IBI_EN_MIN);\n \t\tif (ret)\n \t\t\treturn ret;\n \t} else {\n+\t\tst->gpo_irq[0] = true;\n \t\tret = devm_request_threaded_irq(dev, ret, NULL,\n \t\t\t\t\t\tad4062_irq_handler_thresh,\n \t\t\t\t\t\tIRQF_ONESHOT, indio_dev->name,\n@@ -1347,6 +1353,121 @@ static int ad4062_regulators_get(struct ad4062_state *st, bool *ref_sel)\n \treturn 0;\n }\n \n+static int ad4062_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)\n+{\n+\treturn GPIO_LINE_DIRECTION_OUT;\n+}\n+\n+static int ad4062_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)\n+{\n+\tstruct ad4062_state *st = gpiochip_get_data(gc);\n+\tunsigned int reg_val = value ? AD4062_GP_STATIC_HIGH : AD4062_GP_STATIC_LOW;\n+\n+\tif (offset)\n+\t\treturn regmap_update_bits(st->regmap, AD4062_REG_GP_CONF,\n+\t\t\t\t\t AD4062_REG_GP_CONF_MODE_MSK_1,\n+\t\t\t\t\t FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, reg_val));\n+\telse\n+\t\treturn regmap_update_bits(st->regmap, AD4062_REG_GP_CONF,\n+\t\t\t\t\t AD4062_REG_GP_CONF_MODE_MSK_0,\n+\t\t\t\t\t FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, reg_val));\n+}\n+\n+static int ad4062_gpio_get(struct gpio_chip *gc, unsigned int offset)\n+{\n+\tstruct ad4062_state *st = gpiochip_get_data(gc);\n+\tunsigned int reg_val;\n+\tint ret;\n+\n+\tret = regmap_read(st->regmap, AD4062_REG_GP_CONF, ®_val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (offset)\n+\t\treg_val = FIELD_GET(AD4062_REG_GP_CONF_MODE_MSK_1, reg_val);\n+\telse\n+\t\treg_val = FIELD_GET(AD4062_REG_GP_CONF_MODE_MSK_0, reg_val);\n+\n+\treturn reg_val == AD4062_GP_STATIC_HIGH;\n+}\n+\n+static void ad4062_gpio_disable(void *data)\n+{\n+\tstruct ad4062_state *st = data;\n+\tu8 val = FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, AD4062_GP_DISABLED) |\n+\t\t FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, AD4062_GP_DISABLED);\n+\n+\tregmap_update_bits(st->regmap, AD4062_REG_GP_CONF,\n+\t\t\t AD4062_REG_GP_CONF_MODE_MSK_1 | AD4062_REG_GP_CONF_MODE_MSK_0,\n+\t\t\t val);\n+}\n+\n+static int ad4062_gpio_init_valid_mask(struct gpio_chip *gc,\n+\t\t\t\t unsigned long *valid_mask,\n+\t\t\t\t unsigned int ngpios)\n+{\n+\tstruct ad4062_state *st = gpiochip_get_data(gc);\n+\n+\tbitmap_zero(valid_mask, ngpios);\n+\n+\tfor (unsigned int i = 0; i < ARRAY_SIZE(st->gpo_irq); i++)\n+\t\t__assign_bit(i, valid_mask, !st->gpo_irq[i]);\n+\n+\treturn 0;\n+}\n+\n+static int ad4062_gpio_init(struct ad4062_state *st)\n+{\n+\tstruct device *dev = &st->i3cdev->dev;\n+\tstruct gpio_chip *gc;\n+\tu8 val, mask;\n+\tint ret;\n+\n+\tif (!device_property_read_bool(dev, \"gpio-controller\"))\n+\t\treturn 0;\n+\n+\tgc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);\n+\tif (!gc)\n+\t\treturn -ENOMEM;\n+\n+\tval = 0;\n+\tmask = 0;\n+\tif (!st->gpo_irq[0]) {\n+\t\tmask |= AD4062_REG_GP_CONF_MODE_MSK_0;\n+\t\tval |= FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_0, AD4062_GP_STATIC_LOW);\n+\t}\n+\tif (!st->gpo_irq[1]) {\n+\t\tmask |= AD4062_REG_GP_CONF_MODE_MSK_1;\n+\t\tval |= FIELD_PREP(AD4062_REG_GP_CONF_MODE_MSK_1, AD4062_GP_STATIC_LOW);\n+\t}\n+\n+\tret = regmap_update_bits(st->regmap, AD4062_REG_GP_CONF,\n+\t\t\t\t mask, val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = devm_add_action_or_reset(dev, ad4062_gpio_disable, st);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tgc->parent = dev;\n+\tgc->label = st->chip->name;\n+\tgc->owner = THIS_MODULE;\n+\tgc->base = -1;\n+\tgc->ngpio = 2;\n+\tgc->init_valid_mask = ad4062_gpio_init_valid_mask;\n+\tgc->get_direction = ad4062_gpio_get_direction;\n+\tgc->set = ad4062_gpio_set;\n+\tgc->get = ad4062_gpio_get;\n+\tgc->can_sleep = true;\n+\n+\tret = devm_gpiochip_add_data(dev, gc, st);\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"Unable to register GPIO chip\\n\");\n+\n+\treturn 0;\n+}\n+\n static const struct i3c_device_id ad4062_id_table[] = {\n \tI3C_DEVICE(AD4062_I3C_VENDOR, AD4060_PROD_ID, &ad4060_chip_info),\n \tI3C_DEVICE(AD4062_I3C_VENDOR, AD4062_PROD_ID, &ad4062_chip_info),\n@@ -1435,6 +1556,10 @@ static int ad4062_probe(struct i3c_device *i3cdev)\n \tif (ret)\n \t\treturn dev_err_probe(dev, ret, \"Failed to request i3c ibi\\n\");\n \n+\tret = ad4062_gpio_init(st);\n+\tif (ret)\n+\t\treturn ret;\n+\n \tret = devm_work_autocancel(dev, &st->trig_conv, ad4062_trigger_work);\n \tif (ret)\n \t\treturn ret;\n","prefixes":["v4","9/9"]}