{"id":2175093,"url":"http://patchwork.ozlabs.org/api/1.0/patches/2175093/?format=json","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.0/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20251217-firmware_managed_ep-v3-1-ff871ba688fb@oss.qualcomm.com>","date":"2025-12-17T10:12:45","name":"[v3,1/2] dt-bindings: PCI: qcom,pcie-ep-sa8255p: Document firmware managed PCIe endpoint","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f66a456f0f27494aec5135c193189c895d5c4871","submitter":{"id":90723,"url":"http://patchwork.ozlabs.org/api/1.0/people/90723/?format=json","name":"Mrinmay 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20251217-firmware_managed_ep-v3-1-ff871ba688fb@oss.qualcomm.com>","References":"<20251217-firmware_managed_ep-v3-0-ff871ba688fb@oss.qualcomm.com>","In-Reply-To":"<20251217-firmware_managed_ep-v3-0-ff871ba688fb@oss.qualcomm.com>","To":"Bjorn Helgaas ,\n Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= ,\n Manivannan Sadhasivam , Rob Herring ,\n Krzysztof Kozlowski , Conor Dooley ,\n Philipp Zabel ,\n Bjorn Andersson ","Cc":"linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n Manivannan Sadhasivam ,\n Krishna Chaitanya Chundru ,\n quic_vbadigan@quicinc.com, quic_shazhuss@quicinc.com,\n konrad.dybcio@oss.qualcomm.com,\n Mrinmay sarkar ,\n Rama Krishna ,\n Ayiluri Naga Rashmi ,\n Nitesh Gupta ","X-Mailer":"b4 0.14.2","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1765966367; l=3868;\n i=mrinmay.sarkar@oss.qualcomm.com; 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configuration to enable the PCIe Endpoint controller\non SA8255p which is managed by firmware using power-domain based handling.\n\nSigned-off-by: Mrinmay Sarkar \n---\n .../bindings/pci/qcom,pcie-ep-sa8255p.yaml | 110 +++++++++++++++++++++\n 1 file changed, 110 insertions(+)","diff":"diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..395cd23861ec26c00d51299829f1c60116293cae\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep-sa8255p.yaml\n@@ -0,0 +1,110 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pci/qcom,pcie-ep-sa8255p.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm firmware managed PCIe Endpoint Controller\n+\n+description:\n+ Qualcomm SA8255p SoC PCIe endpoint controller is based on the Synopsys\n+ DesignWare PCIe IP which is managed by firmware.\n+\n+maintainers:\n+ - Manivannan Sadhasivam \n+\n+properties:\n+ compatible:\n+ const: qcom,pcie-ep-sa8255p\n+\n+ reg:\n+ items:\n+ - description: Qualcomm-specific PARF configuration registers\n+ - description: DesignWare PCIe registers\n+ - description: External local bus interface registers\n+ - description: Address Translation Unit (ATU) registers\n+ - description: Memory region used to map remote RC address space\n+ - description: BAR memory region\n+ - description: DMA register space\n+\n+ reg-names:\n+ items:\n+ - const: parf\n+ - const: dbi\n+ - const: elbi\n+ - const: atu\n+ - const: addr_space\n+ - const: mmio\n+ - const: dma\n+\n+ interrupts:\n+ items:\n+ - description: PCIe Global interrupt\n+ - description: PCIe Doorbell interrupt\n+ - description: DMA interrupt\n+\n+ interrupt-names:\n+ items:\n+ - const: global\n+ - const: doorbell\n+ - const: dma\n+\n+ iommus:\n+ maxItems: 1\n+\n+ reset-gpios:\n+ description: GPIO used as PERST# input signal\n+ maxItems: 1\n+\n+ wake-gpios:\n+ description: GPIO used as WAKE# output signal\n+ maxItems: 1\n+\n+ power-domains:\n+ maxItems: 1\n+\n+ dma-coherent: true\n+\n+ num-lanes:\n+ default: 2\n+\n+required:\n+ - compatible\n+ - reg\n+ - reg-names\n+ - interrupts\n+ - interrupt-names\n+ - reset-gpios\n+ - power-domains\n+\n+additionalProperties: false\n+\n+examples:\n+ - |\n+ #include \n+ #include \n+ soc {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+ pcie1_ep: pcie-ep@1c10000 {\n+ compatible = \"qcom,pcie-ep-sa8255p\";\n+ reg = <0x0 0x01c10000 0x0 0x3000>,\n+ <0x0 0x60000000 0x0 0xf20>,\n+ <0x0 0x60000f20 0x0 0xa8>,\n+ <0x0 0x60001000 0x0 0x4000>,\n+ <0x0 0x60200000 0x0 0x100000>,\n+ <0x0 0x01c13000 0x0 0x1000>,\n+ <0x0 0x60005000 0x0 0x2000>;\n+ reg-names = \"parf\", \"dbi\", \"elbi\", \"atu\", \"addr_space\", \"mmio\", \"dma\";\n+ interrupts = ,\n+ ,\n+ ;\n+ interrupt-names = \"global\", \"doorbell\", \"dma\";\n+ reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;\n+ wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;\n+ dma-coherent;\n+ iommus = <&pcie_smmu 0x80 0x7f>;\n+ power-domains = <&scmi6_pd 1>;\n+ num-lanes = <4>;\n+ };\n+ };\n","prefixes":["v3","1/2"]}